參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 123/165頁
文件大小： 1895K
代理商： TLV320AIC36IZQE
MCLK
BCLK
DIN
PLL_CLK
DAC_CLK
DAC_MOD_CLK
ADC_CLK
ADC_MOD_CLK
÷M
CDIV_CLKIN
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
DOUT
Page 0 Reg23[1:0]
M=1,2,3,...127,128
Page 0 Reg26[6:0]
Page 0
Reg 120
Page 0
Reg 121
Page 0
Reg 122
Page 0
Reg 123
Page 0
Reg 124
Page 0
Reg 125
Page 0
Reg 126
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
D(6:0) from 1 to 128. The BDIV_CLKIN can itself be configured to be one of DAC_CLK, DAC_MOD_CLK,
ADC_CLK or ADC_MOD_CLK by configuring the BDIV_CLKIN mux in Page 0, Register 27, D(1:0).
Additionally a general purpose clock can be driven out on DOUT or a GPIO pin. This clock can be a
divided down version of CDIV_CLKIN. The value of this clock divider can be programmed from 1 to 128
by writing to Page 0, Register 24, D(6:0). The CDIV_CLKIN can itself be programmed as one of the clocks
among the list shown in Figure 5-34. This can be controlled by programming the mux in Page 0, Register
23, D(2:0).
Figure 5-34. General-Purpose Clock Output Options
Table 5-20. Maximum TLV320AIC36 Clock Frequencies
Maximum Frequency
Clock
(DVDD=1.8V)
(DVDD=1.5V)
CODEC_CLKIN
110MHz
104MHz
ADC_CLK
60MHz
34.6MHz
ADC_miniDSP_CLK
30MHz
17.3MHz
ADC_MOD_CLK
6.758MHz
5.77MHz
ADC_FS
0.192MHz
0.18MHz
DAC_CLK
60MHz
34.6MHz
DAC_miniDSP_CLK
60MHz
34.6MHz
DAC_MOD_CLK
6.758MHz
5.77MHz
DAC_FS
0.192MHz
0.18MHz
BDIV_CLKIN
50MHz
34.6MHz
CDIV_CLKIN
110MHz
104MHz
5.16.1 PLL
The TLV320AIC36 has an on chip PLL with fractional multiplication to generate the clock frequency
needed by the audio ADC, DAC, and Digital Signal Processing blocks. The programmability of the PLL
allows operation from a wide variety of clocks that may be available in the system.
60
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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