參數(shù)資料
型號(hào)： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 141/165頁
文件大小： 1895K
代理商： TLV320AIC36IZQE
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
3D 01 # Left, Right ADC not muted digital gain=0dB (-0.1dB steps) # adc on: 52=00, adc off:
52=88 w 30 52 88 # ADCL, ADCR digital gain (7b signed 0.5dB steps) w 30 53 00 w 30 54 00 # L
AGC, R AGC disabled, target=-5.5dB w 30 56 00 w 30 5E 00 # PRI_BCLK_OUT=internally generated
BCLK, SEC_BCLK_OUT=Primary BCLK, # PRI_WCLK_OUT= ADC_FS clock, SEC_WCLK=Primary WCLK,
PRI_DOUT=DOUT from CODEC w 30 21 10 # ADC filter output to I2S, I2S to DAC filter input, BCLK
not inverted, BCLK WCLK active even when CODEC is PD w 30 1B 06 # reduce hp,dac,lo,rec currents
on pg2p0 # ulp, lp: ( 7a=ff, reduce max, 7a=55, reduce by 1/2) w 30 00 02 w 30 7a ff # dac
current control w 30 6B 80 # charge pump on (71=00 disabled, 71=01 clk=BCLK, 72=73=0b Bclk/6) w
30 00 02 w 30 72 0b w 30 73 0b # LADC,RADC powerup, DIG_MIC_INP, LDIG_MIC,RDIG_MIC disabled,
soft-step disabled # adc on: 51=c2, adc off: 51=02 w 30 00 00 w 30 51 02 # LDAC,RDAC
powerup,left data to LDAC, right data to RDAC, soft-step disble (d6), L->R, R->L (ea), L->L, L-
>R (da) w 30 3F d6 # Dac auto-mute disable, left,right dac not muted, left,right dac volume
control independent w 30 40 00 # Modulator start-up sequence w 30 00 fd w 30 0d 0d w 30 04 20 w
30 0d 00 # LDAC, RDAC digital gain 8 bit signed (0.5dB steps) f4=-6dB # ulp 41=fc, f2=fc, lp:
41=00,42=00 w 30 00 00 w 30 41 fc w 30 42 fc # ANALOG ADC CODE
################################### # Briefly connect internal CM to LEFT and RIGHT MIC PGA #
for CM startup in differential mode w 30 00 01 w 30 34 00 w 30 36 80 w 30 37 00 w 30 39 80 #
connect mic1p,1m to pga leftp (34=20) leftm (36=20) 20k # connect mic2p,2m to pga rightp
(37=20) rightm (39=20) 20k # connect extmic_p,m to pga leftp (34=08) leftm (36=08) 20k #
connect lineinl to pgalp 34=80, cml to pgalm 36=80 # connect lineinr to pgarp 37=80, cmr to
pgarm 39=80 w 30 00 01 w 30 34 20 w 30 36 20 w 30 37 20 w 30 39 20 # lineinr, lineinl (c0) to
internal cm if adc is on (00) floating w 30 3A 00 # LADC,RADC PGA gain=0dB (0.5dB steps),
CM=0.9V # ulp: 0A=40, lp: 0A=00 w 30 3B 00 w 30 3C 00 w 30 0A 40 w 30 00 02 # select LINE2LP,
LINE2RP, 28=14 SE in bypass amp w 30 00 02 w 30 28 14 # ANALOG DAC CODE
################################### # dacl,dacr power up, short ckt protect output drivers
enabled # c0=both dacs, 80=ldac, 40=rdac w 30 00 02 w 30 25 c0 w 30 26 04 # BCLK powerup,
divide 4 w 30 00 00 w 30 1C 84 # pop reduction w 30 00 02 w 30 2A 34 # modulator taps
(2,4,6,8,a or 1,2,3,4,5 or 0,3,5,7,9,c) w 30 00 00 w 30 72 30 w 30 73 75 w 30 74 c9 # dac to
line out -3dB gain w 30 00 02 #w 30 56 09 #w 30 52 86 #w 30 50 f6 #w 30 5d 09 #w 30 5c 86 #w 30
5a f6 #enable HPR gain=-3dB, #connect to LINEL (2d) PGAL(2e) DACL (2f) LINER (30) PGAR (31)
DACR
(32), 80=0 dB f5=-78 dB, f6=mute # ulp 32=86, 36=86, lp: ,32=84, 36=84 w 30 00 02 w 30 24 00 w
30 32 86 w 30 33 09 #enable HPL gain=-3dB # connect to LINEL (34) PGAL (35) DACL (36) LINER
(37) PGAR (38) DACR (39), -3 dB w 30 36 86 w 30 3a 09 #dac to rec amps w 30 00 02 #w 30 3d 86
#w 30 41 09 #w 30 47 86 #w 30 48 09
Copyright 2009–2010, Texas Instruments Incorporated
APPLICATION INFORMATION
77
Product Folder Link(s): TLV320AIC36
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