- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98254 > TLV320AIC36IZQE (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PBGA80 PDF資料下載
參數(shù)資料
| 型號(hào)： | TLV320AIC36IZQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, VFBGA-80 |
| 文件頁(yè)數(shù)： | 112/165頁(yè) |
| 文件大小： | 1895K |
| 代理商： | TLV320AIC36IZQE |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)當(dāng)前第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
Table 5-17. DAC Interpolation Filter C, Specification
Parameter
Condition
Value (Typical)
Units
Filter gain pass band
0 … 0.35 Fs
±0.03
dB
Filter gain stop band
0.60 … 1.4 Fs
–43
dB
Filter group delay
13/Fs
s
5.12 DAC Output Drivers
5.12.1 Analog Fully Differential Line Output Drivers
The TLV320AIC36 has two fully differential line output drivers, each capable of driving a 10k
differential
load. Each driver can connect to the left or the right DAC, the left or the right ADC PGA output, the left or
right line input, or any combination of the six. The design includes extensive capability to adjust signal
levels independently before any mixing occurs, beyond that already provided by the PGA gain and the
DAC digital volume control. Note that since both left and right channel signals are routed to all output
drivers, a mono mix of any of the stereo signals can easily be obtained by setting the volume controls of
both left and right channel signals to –6 dB and mixing them. Undesired signals can also be disconnected
from the mix as well through register control.
The TLV320AIC36 includes an output level control on each output driver with limited gain adjustment from
0 dB to +9 dB. The output driver circuitry in this device are designed to provide a low distortion output
while playing full-scale stereo DAC signals at a 0 dB gain setting. However, a higher amplitude output can
be obtained at the cost of increased signal distortion at the output. This output level control allows the user
to make this tradeoff based on the requirements of the end equipment. Note that this output level control
is not intended to be used as a standard output volume control. It is expected to be used only sparingly for
level setting, that is, adjustment of the full-scale output range of the device.
Each differential line output driver can be powered down independently of the others when it is not needed
in the system. When placed into powerdown through register programming, the driver output pins will be
placed into a high-Z, high-impedance state.
The signal routing for the line level drivers is configured using Page 2, Registers 80 through 93
5.12.2 Analog High-Power Output Drivers
The TLV320AIC36 includes four single-ended high power output drivers arranged as two stereo pairs.
These output drivers are capable of driving 0.89 Vrms each into a 16-
load if one pair is enabled or 0.5
Vrms each into 16-
if both pairs are enabled. The volume control and mixing blocks for the high-power
output drivers are effectively identical to those of the line-level drivers. Note that each of these drivers
have a output level control block like those included with the line output drivers, allowing gain adjustment
up to +9 dB on the output signal. As in the previous case, this output level adjustment is not intended to
be used as a standard volume control, but instead is included for additional full-scale output signal level
control. In order to drive 0.89 Vrms for a full-scale DAC output into the load, the output level adjustment
must be set to +2 dB.
The high power output drivers include additional circuitry to avoid artifacts on the audio output during
power-on and power-off transient conditions. The power-up delay time for the high power output drivers is
programmable over a wide range of time delays, from instantaneous up to 4-sec, using Page-2/Reg-42.
When these output drivers are powered down, they can be placed into a variety of output conditions based
on register programming. If lowest power operation is desired, then the outputs can be placed into a
tri-state condition, and all power to the output stage is removed. However, this generally results in the
output nodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the
pins. This then results in a longer delay requirement to avoid output artifacts during driver power-on. In
order to reduce this required power-on delay, the TLV320AIC36 includes an option for the output pins of
the drivers to be weakly driven to the AGND level they would normally rest at when powered with no
signal applied.
50
APPLICATION INFORMATION
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV320DAC23IPW | SERIAL INPUT LOADING, 32-BIT DAC, PDSO28 |
| TLV320DAC23IGQER | SERIAL INPUT LOADING, 32-BIT DAC, PBGA80 |
| TLV320DAC23PWR | SERIAL INPUT LOADING, 32-BIT DAC, PDSO28 |
| TLV320DAC23RHDR | SERIAL INPUT LOADING, 32-BIT DAC, PQCC28 |
| TLV320DAC23RHDG4 | SERIAL INPUT LOADING, 32-BIT DAC, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC36IZQER | 功能描述:接口—CODEC Low Pwr Stereo Aud Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320ALC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC |
| TLV320ALC31 | 制造商:BB 制造商全稱:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| TLV320DA26IRHBG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Lo-Pwr Ster DAC w/Hdphn/Spkr Amp RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO D/A CONVERTER, 8-TO 96KHZ WITH INTERGRATED HEADPHONE AMPLIFIER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。