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TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 106:
Right-AGC New Programmable Decay Time Register
(1)
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
Decay Time Register Selection
0: Decay time for the right AGC is generated from register 29.
1: Decay time for the right AGC is generated from this register.
Baseline AGC Decay time
00: Right-AGC decay time = 50 ms
01: Right-AGC decay time = 150 ms
10: Right-AGC decay time = 250 ms
11: Right-AGC decay time = 350 ms
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC decay time = 1
001: Multiplication factor for the baseline AGC decay time = 2
010: Multiplication factor for the baseline AGC decay time = 4
011: Multiplication factor for the baseline AGC decay time = 8
100: Multiplication factor for the baseline AGC decay time = 16
101: Multiplication factor for the baseline AGC decay time = 32
110: Multiplication factor for the baseline AGC decay time = 64
111: Multiplication factor for the baseline AGC decay time = 128
Reserved. Write only zeros to these register bits.
D6–D5
R/W
00
D4–D2
R/W
000
D1–D0
R/W
00
(1)
Decay time is limited based on the NADC ratio that is selected. For
NADC = 1, maximum decay time = 4 seconds
NADC = 1.5, maximum decay time = 5.6 seconds
NADC = 2, maximum decay time = 8 seconds
NADC = 2.5, maximum decay time = 9.6 seconds
NADC = 3 or 3.5, maximum decay time = 11.2 seconds
NADC = 4 or 4.5, maximum decay time = 16 seconds
NADC = 5, maximum decay time = 19.2 seconds
NADC = 5.5 or 6, maximum decay time = 22.4 seconds
Page 0 / Register 107:
New Programmable ADC Digital Path and I
2
C Bus Condition Register
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
Left-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
Right-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
ADC Decimation Filter configuration
00: Left and right digital microphones are used.
01: Left digital microphone and right analog microphone are used.
10: Left analog microphone and right digital microphone are used.
11: Left and right analog microphones are used.
ADC Digital Output to Programmable Filter Path Selection
0: No additional programmable filters other than the HPF are used for the ADC.
1: The programmable filter is connected to ADC output if both DACs are powered down.
I
2
C Bus Condition Detector
0: Internal logic is enabled to detect an I
2
C bus error, and clears the bus error condition.
1: Internal logic is disabled to detect an I
2
C bus error.
Reserved. Write only zero to this register bit.
I
2
C Bus Error Detection Status
0: I
C bus error is not detected.
1: I
2
C bus error is detected. This bit is cleared by reading this register.
D6
R/W
0
D5–D4
R/W
00
D3
R/W
0
D2
R/W
0
D1
D0
R
R
0
0
Copyright 2007, Texas Instruments Incorporated
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