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TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 17:
MIC3L_x and MIC3R_x to Left-ADC Control Register
READ/
WRITE
R/W
RESET
VALUE
1111
BIT
DESCRIPTION
D7–D4
MIC3L_x Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3L_x to the
left-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3L_x is not connected to the left-ADC PGA.
MIC3R_x Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3R_x to the
left-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3R_x is not connected to the left-ADC PGA.
D3–D0
R/W
1111
Page 0 / Register 18:
MIC3L_x and MIC3R_x to Right-ADC Control Register
READ/
WRITE
R/W
RESET
VALUE
1111
BIT
DESCRIPTION
D7–D4
MIC3L_x Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3L_x to the
right-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3L_x is not connected to the right-ADC PGA.
MIC3R_x Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3R_x to the
right-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3R_x is not connected to the right-ADC PGA.
D3–D0
R/W
1111
Copyright 2007, Texas Instruments Incorporated
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