參數(shù)資料
型號: TLV320AIC34_1
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 四通道,低功耗音頻編解碼器的便攜式音頻/電話
文件頁數(shù): 63/94頁
文件大?。?/td> 905K
代理商: TLV320AIC34_1
www.ti.com
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 25:
MICBIAS_x Control Register
READ/
WRITE
R/W
RESET
VALUE
00
BIT
DESCRIPTION
D7–D6
MICBIAS_x Level Control
00: MICBIAS_x output is powered down.
01: MICBIAS_x output is powered to 2 V.
10: MICBIAS_x output is powered to 2.5 V.
11: MICBIAS_x output is connected to AVDD.
Digital Microphone Control
00: If digital MIC is enabled, both left and right digital MICs are available.
01: If digital MIC is enabled, left digital MIC and right ADC are available.
10: If digital MIC is enabled, left ADC and right digital MIC are available.
11: Reserved. Do not write this sequence to these register bits.
Reserved. Do not write to this register bit.
Reserved. Write only zeros to these register bits.
D5–D4
R/W
00
D3
R
R
0
D2–D0
XXX
Page 0 / Register 26:
Left-AGC Control Register A
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
Left-AGC Enable
0: Left AGC is disabled.
1: Left AGC is enabled.
Left-AGC Target Level
000: Left-AGC target level = –5.5 dB
001: Left-AGC target level = –8 dB
010: Left-AGC target level = –10 dB
011: Left-AGC target level = –12 dB
100: Left-AGC target level = –14 dB
101: Left-AGC target level = –17 dB
110: Left-AGC target level = –20 dB
111: Left-AGC target level = –24 dB
Left-AGC Attack Time
These time constants
(1)
are not accurate when double-rate audio mode is enabled.
00: Left-AGC attack time = 8 ms
01: Left-AGC attack time = 11 ms
10: Left-AGC attack time = 16 ms
11: Left-AGC attack time = 20 ms
Left-AGC Decay Time
These time constants
(1)
are not accurate when double-rate audio mode is enabled.
00: Left-AGC decay time = 100 ms
01: Left-AGC decay time = 200 ms
10: Left-AGC decay time = 400 ms
11: Left-AGC decay time = 500 ms
D6–D4
R/W
000
D3–D2
R/W
00
D1–D0
R/W
00
(1)
Time constants are valid when double-rate audio is not enabled. The values would change if double-rate audio is enabled.
Page 0 / Register 27:
Left-AGC Control Register B
READ/
WRITE
R/W
RESET
VALUE
1111 111
BIT
DESCRIPTION
D7–D1
Left-AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
1110 110: Maximum gain = 59 dB
1110 111–1111 111: Maximum gain = 59.5 dB
Reserved. Write only zero to this register bit.
D0
R/W
0
Copyright 2007, Texas Instruments Incorporated
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TLV320AIC34
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