參數(shù)資料
型號(hào): TLV320AIC3110IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 112/126頁
文件大?。?/td> 1528K
代理商: TLV320AIC3110IRHBR
SLAS647 – DECEMBER 2009
www.ti.com
Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
000: ADC_WCLK is obtained from GPIO1 pin.
001: Reserved.
010: Reserved.
011: Reserved
100: Reserved.
101: Reserved.
110: Reserved.
111: Reserved.
D4
R/W
0
Reserved
D3
R/W
0
0: Primary BCLK is fed to codec serial-interface and ClockGen blocks.
1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks.
D2
R/W
0
0: Primary WCLK is fed to codec serial-interface block.
1: Secondary WCLK is fed to codec serial-interface block.
D1
R/W
0
0: ADC_WCLK used in the codec serial-interface block is the same as DAC_WCLK.
1: ADC_WCLK used in the codec serial-interface block = ADC_WCLK.
D0
R/W
0
0: Primary DIN is fed to codec serial-interface block.
1: Secondary DIN is fed to codec serial-interface block.
Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
D6
R/W
0
0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
D5–D4
R/W
00
00: Primary WCLK output = internally generated DAC_fS
01: Primary WCLK output = internally generated ADC_fS clock
10: Primary WCLK output = secondary WCLK
11: Reserved
D3–D2
R/W
00
00: Secondary WCLK output = primary WCLK
01: Secondary WCLK output = internally generated DAC_fS clock
10: Secondary WCLK output = internally generated ADC_fS clock
11: Reserved
D1
R/W
0
0: Primary DOUT = DOUT from codec serial-interface block
1: Primary DOUT = secondary DIN
D0
R/W
0
0: Secondary DOUT = primary DIN
1: Secondary DOUT = DOUT from codec serial interface block
Page 0 / Register 34 (0x22): I2C Bus Condition
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Reserved. Write only the reset value to these bits.
D5
R/W
0
0: I2C general-call address is ignored.
1: Device accepts I2C general-call address.
D4–D0
R/W
0 0000
Reserved. Write only zeros to these bits.
Page 0 / Register 35: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Write only zeros to these bits.
86
REGISTER MAP
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3110
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