參數(shù)資料
型號(hào)： TLV320AD11APZ
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： 3.3 V INTEGRATED ADSL OVER POTS CODEC
中文描述： 3.3伏集成ADSL POTS和編解碼器
文件頁(yè)數(shù)： 4/28頁(yè)
文件大小： 412K
代理商： TLV320AD11APZ
TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions(Continued)
TERMINAL
NAME
DVDD_BF
I/O
DESCRIPTION
NO.
26
I
Digital I/O buffer supply
DVDD_CLK
44
I
Digital clock supply
DVDD_LG
47
I
Digital logic supply
DVDD_RX
15
I
Receive channel digital power supply
DVDD_DAC
57
I
Digital power supply for DAC
DVSS
9, 58
I
Digital ground
DVSS_BF
27
I
Digital I/O buffer ground
DVSS_CLK
43
I
Digital clock ground
DVSS_LG
46
I
Digital logic ground
DVSS_RX
16
I
Receive channel ground
DVSS_DAC
56
I
DAC ground
ECM
79
O
EC output minus
ECP
78
O
EC output plus
FS
38
I
Frame sync input
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
8
7
6
5
4
3
2
1
O
General-purpose output port
INT
40
O
Data rate clock (INT is 4.4 MHz when OSEN=1, 2.2 MHz when OSEN=0)
NC
10, 14, 74,
75, 76, 77,
80, 85, 91,
97
No connection. All the NC pins should be left open.
OE
50
I
Parallel port output enable from host processor
OE_SYNC
99
I
OE synchronized input. A high input will optimize the read operation from keep-out zone. The default
state of this pin is low. See Figure 5 for details.
ONE_WE
98
I
TX and EC write combined input. A high on this pin allows pin 48, WETX, to be used to write to both the
EC and TX channels. In this case, after a hardware reset or write to SCR14[0], the first low-going pulse of
WETX will be a write to TX channel and the second one will be a write to EC channel. The default state of
this pin is low.
OSEN
39
I
Over-sampling enable input. OSEN=1 enables over-sampling mode (INT = 4.4 MHz).
PWDN
53
I
Power-down input. When PWDN=0, device is in normal operating mode. When PWDN=1, device is in
power-down mode.
REFM
89
O
Decoupling reference REF voltage minus. Add 10
μ
F tantalum and 0.1
μ
F ceramic capacitors to
AVSS_REFP. The nominal dc voltage at this terminal is 0.5 V. See figure 9 for detail.
REFP
88
O
Decoupling reference REF voltage plus. Add 10
μ
F tantalum and 0.1
μ
F ceramic capacitors to
AVSS_REFM. The nominal dc voltage at this terminal is 2.5 V.. See figure 9 for detail.
RESET
52
I
H/W system reset. An low level will reset the device.
RXM
96
I
Receive RX input minus. RXM is self-biased to AVDD_FIL_RX/2.
RXP
95
I
Receive RX input plus. RXP is self-biased to AVDD_FIL_RX/2.
SCLK/READY
37
O
If CONFIG2 (pin 100) is low, this pin is serial clock output. If CONFIG2 is high, it indicates the period in
which parallel data can be transferred.
SDI
36
I
Serial data input
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