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| 型號： | TLV320AD11APZ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | 3.3 V INTEGRATED ADSL OVER POTS CODEC |
| 中文描述： | 3.3伏集成ADSL POTS和編解碼器 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大小： | 412K |
| 代理商： | TLV320AD11APZ |
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TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CONFIG2=0 or floating
CLKIN
(35.328 MHz)
(Input)
INT
(OSEN = 0)
(Output)
INT
(OSEN = 1)
(Output)
CLKOUT
(Output)
CS
(Input)
(see Note A)
OE
(RXADC)
(Input)
(see Note A)
WETX
(TXDAC)
(Input)
(see Note B)
WEEC
(TXDAC)
(Input)
(see Note B)
D0–D15
(Input/Output)
Keep-Out Zones
tc1
td1
tw1
tc2
tc2
tc3
td2
tw2
td3
td9
tw3
td3
td9
tsu2
tw4
th2
tsu1
th1
td5
td4
Access Zone
Access Zone
Access Zone
Access Zone
Access Zone
NOTES: A. CS AND OE may fall/rise together or be skewed from each other. It does not matter which falls/rises first. However, td4 is referenced
from whichever falls last, and td5 is referenced from whichever rises first. CS can be connected to low if the parallel bus is not shared.
B. CS and WETX/WEEC may fall together or be skewed from each other. But the rising edge of WETX and WEEC should occur prior
to the rising edge of CS.
C. The minimum update rate for TX and EC channel is 276 kHz in normal mode, and 552 kHz in over-sampling mode. The write
operation for Tx and EC can occur at any time, if they do not conflict with each other or the Rx read cycle.
Figure 2. Parallel Timing Diagram
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