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參數(shù)資料
| 型號(hào)： | TLC34075-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 48/52頁 |
| 文件大小： | 284K |
| 代理商： | TLC34075-135 |
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C
–
1
Appendix C
SCLK Frequency > VCLK Frequency
The VCLK and SCLK outputs generated by the TLC34075 are both free-running clocks. The video control
signals (i.e., HSYNC, VSYNC, and BLANK) are normally generated from VCLK, and a fixed relationship
between the video control signals and VCLK can therefore be expected. The TLC34075 samples and
latches the BLANK input on the falling edge of VCLK. It then looks at the LOAD signal to determine when
to disable or enable SCLK at its output terminal. The decision is deterministic when the SCLK frequency
is greater than or equal to the VCLK frequency. However, when the SCLK frequency is less than the VCLK
frequency, the appearance of the SCLK waveform at its output terminal when BLANK is sampled low on the
VCLK falling edge can vary (see Figures C
–
1 and C
–
2).
To avoid this variation in the SCLK output waveform, the SCLK and VCLK frequencies should be chosen
so that HTOTAL is evenly divisible by the ratio of (VCLK frequency:SCLK frequency); that is,
remainder of
HTOTAL
VCLK frequency
SCLK frequency
0.
For example, if HTOTAL is even, VCLK frequency = DOTCLK frequency/8, and SCLK frequency =
DOTCLK frequency/16, then the formula above is satisfied. NOTE: When HTOTAL starts at zero (as in the
TMS340x0 GSP), then the formula becomes
remainder of
(HTOTAL
VCLK frequency
SCLK frequency
1)
0.
VCLK
BLANK
LOAD
(Internal Signal
for Data Latch)
SCLK at
Output Terminal
Figure 21. VCLK and SCLK Phase Relationship (Case 1)
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相關(guān)代理商/技術(shù)參數(shù) |
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| TLC34075-135AFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLC34075-135AFNR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
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| TLC34075-66 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TLC34075-66AFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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