參數(shù)資料
型號: TLC34075-135
廠商: Texas Instruments, Inc.
英文描述: Video Interface Palette
中文描述: 視頻接口面板
文件頁數(shù): 38/52頁
文件大?。?/td> 284K
代理商: TLC34075-135
PARAMETER
UNIT
3
6
3.6 Switching Characteristics (Cont
d.)
TL34075-110, TLC34075-135
TLC34075-110
MIN
TYP
TLC34075-135
MIN
TYP
MAX
MAX
SCLK frequency (see Note 10)
VCLK frequency
Enable time, RD low to D<0:7> valid
Disable time, RD high to D<0:7> disabled
Valid time, D<0:7> valid after RD high
Propagation delay, SFLAG/NFLAG
to SCLK
high (see Note 11)
Delay time, RD low to D<0:7> starting to turn
on
Delay time, selected input clock high/low to
DOTCLK (internal signal) high/low
Delay time, DOTCLK high/low to VCLK
high/low
Delay time, VCLK high/low to SCLK high/low
Delay time, DOTCLK high/low to SCLK
high/low
Delay time, DOTCLK high to IOR/IOG/IOB
active (analog output delay time) (seeNote
12)
Analog output settling time (see Note 13)
Delay time, DOTCLK high to HSYNCOUT and
VSYNCOUT valid
Pulse duration, SCLK high (see Note 11)
Analog output rise time (see Note 14)
Analog output skew
NOTES: 10.SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns.
11.This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
12.Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
13.Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
±
1 LSB (settling time does not include clock and data feedthrough).
14.Measured between 10% and 90% of the full-scale transition.
85
85
40
17
85
85
40
17
MHz
MHz
ns
ns
ns
ten1
tdis1
tv1
5
5
tPLH1
0
20
0
20
ns
td1
5
5
ns
td2
7
7
ns
td3
6
6
ns
td4
0
5
0
5
ns
td5
8
8
ns
td6
20
20
ns
td7
6
6
ns
td8
3
3
ns
tw6
tr
15
55
15
55
ns
ns
ns
2
2
0
2
0
2
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