
PARAMETER
UNIT
Clock cycle time
tcyc
ns
ns
Pulse duration, clock low
tw4
ns
Pulse duration, clock high
tw3
3
–
4
3.5 Timing Requirements
TLC34075-66
MIN
TLC34075-85
MIN
TLC34075-110
MIN
TLC34075-135
MIN
MAX
MAX
MAX
110
MAX
135
DOTCLK frequency
CLK0 frequency for VGA
pass-through mode
66
85
MHz
66
85
85
85
MHz
TTL
ECL
15.2
15.2
11.8
11.8
9.1
9.1
7.4
7.4
tsu1
Setup time, RS<0:3>
valid before RD or WR
↓
Hold time, RS<0:3> valid
after RD or WR
↓
Setup time, D<0:7> valid
before WR
↑
Hold time, D<0:7> valid
after WR
↑
Setup time, VGA<0:7> and
HSYNC, VSYNC, and
VGABLANK valid before
CLK0
↑
Hold time, VGA<0:7> and
HSYNC, VSYNC, and
VGABLANK valid after CLK0
↑
Setup time, P<0:31> valid
before SCLK
↑
Hold time, P<0:31> valid after
SCLK
↑
Setup time, HSYNC, VSYNC,
and BLANK valid before
VCLK
↓
Hold time, HSYNC, VSYNC,
and BLANK valid after VCLK
↓
Pulse duration, RD or WR low
Pulse duration, RD or WR high
10
10
10
10
ns
th1
10
10
10
10
ns
tsu2
35
35
35
35
ns
th2
0
0
0
0
ns
tsu3
2
2
2
2
ns
th3
2
2
2
2
ns
tsu4
2
2
2
0
ns
th4
5
5
5
5
ns
tsu5
5
5
5
5
ns
th5
2
2
2
2
ns
tw1
tw2
50
30
4.5
5.5
4.5
5.5
50
30
4
4
4
4
50
30
3.5
3.5
3.5
3.5
50
30
3
3
3
3
ns
ns
TTL
ECL
TTL
ECL
tw5
Pulse duration, SFLAG/NFLAG
high (see Note 4)
NOTES: 3. TTL input signals are 0 to 3 V with less than 3 ns rise/fall time between the 10% and 90% levels unless
otherwise specified. ECL input signals are VDD
–
1.8 V to VDD
–
0.8 V with less than 2 ns rise/fall time between
the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and 90% signal
levels. Analog output loads are less than 10 pF. D<0:7> output loads are less than 50 pF. All other output loads
are less than 50 pF unless otherwise specified.
4. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
30
30
30
30
ns