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| 型號： | TLC34058-110M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 256 ?24 COLOR PALETTE |
| 中文描述： | 256？24調(diào)色板 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 322K |
| 代理商： | TLC34058-110M |
TLC34058-110M
256
×
24 COLOR PALETTE
SGLS075 – JANUARY 1994
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, R
set
= 523
, V
ref
= 1.235 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
%
%
VDD
Iref
Input reference current
10
kSVR
Supply voltage rejection ratio
f = 1 kHZ,
See Figure 4
C8 = 0.1
μ
F,
0.5
IDD
Supply current
VDD = 5 V,
VDD = 5.5 V,
VI = VCC
VI = 2.4 V
VI = 0 V
VI = 0.8 V
f = 1 MHz,
TA = 20
°
C
TA = –55
°
C
195
mA
550
IIH
High-level input current
CLK, CLK
10
μ
A
μ
A
μ
A
μ
A
pF
Other inputs
10
IIL
Low-level input current
CLK, CLK
–10
Other inputs
–10
Ci
Ci(CLK)
VOH
VOL
IOZ
zo
Co
* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
All typical values are at TA = 25
°
C.
Input capacitance, digital
VI(PP) = 1 V
VI(PP) = 1 V
4
20*
Input capacitance, CLK, CLK
f = 1 MHz,
IOH = –800
μ
A
IOL = 6.4 mA
4
20*
pF
High-level output voltage, D0–D7
2.4
V
Low-level output voltage, D0–D7
0.4
V
μ
A
k
pF
High-impedance-state output current
10
Output impedance
50
Output capacitance (f = 1 MHz, IO = 0)
13
20*
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, R
set
= 523
, V
ref
= 1.235 V (see Note 2)
MIN
MAX
UNIT
Clock frequency
110
MHz
LD frequency
Setup time, R/W, C0, C1 high before CE
↓
Setup time, write data before CE
↑
Setup time, pixel and control
Hold time, R/W, C0, C1 high after CE
↓
Hold time, write data after CE
↑
Hold time, pixel and control
27.5
MHz
tsu1
tsu2
tsu3
th1
th2
th3
tw1
tw2
tw3
tw4
tw5
tw6
tc1
tc2
See Figures 1 and 2.
NOTE 2: TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are VDD –1.8 V to
VDD –0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points are
at the 50% signal level. Analog output loads are less than 10 pF. D0–D7 output loads are less than 40 pF.
0
ns
35
ns
3
ns
15
ns
3
ns
2
ns
Pulse duration, CE low
50
ns
Pulse duration, CE high
25
ns
Pulse duration, CLK high
4
ns
Pulse duration, CLK low
4
ns
Pulse duration, LD high
15
ns
Pulse duration, LD low
15
ns
Clock cycle time
9.09
ns
LD cycle time
36.36
ns
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