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參數(shù)資料
| 型號(hào)： | THS0842PFB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT |
| 中文描述： | 雙輸入，8位，40 MSPS的低功耗模擬數(shù)字轉(zhuǎn)換器單路或雙路并行總線輸出 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大小： | 479K |
| 代理商： | THS0842PFB |
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THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions with f
CLK
= 80 MSPS and use
of internal voltage references, AV
DD
= DV
DD
= DRV
DD
= 3 V, T
A
= –40
°
C to 80
°
C, dual output bus mode
(unless otherwise noted) (continued)
dynamic performance
PARAMETER
TEST CONDITIONS
MIN
6.6
TYP
6.9
MAX
UNIT
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
See Note 6
Effective number of bits, ENOB
6.4
6.8
Bits
6.4
6.8
41.5
43.5
Signal-to-total harmonic distortion + noise, S/(THD+N)
40
42.5
dB
40
42.5
–51
–46
Total harmonic distortion (THD)
–48.5
–44
dB
–48.5
–44
48
53
Spurious free dynamic range (SFDR)
47
52.2
dB
46
52
Analog input full-power bandwidth, BW
600
MHz
Intermodulation distortion
f1 = 1 MHz, f2 = 1.02 MHz
50
dBc
I/Q channel crosstalk
Based on analog input voltage of –1 dBFS referenced to a 1.3 Vpp full-scale input range.
NOTE 6: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which
an extra 3 dB attenuation is observed in the reconstructed output signal.
AVDD = DVDD = DRVDD = 3.3 V
–52
dBc
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
flk
fclk
Maximum clock rate (see Note 7)
80
Minimum clock rate
10
kHz
td(O)
th(O)
Output delay time (see timing diagram)
CL = 10 pF
9
ns
Output hold time from COUT or COUT to data invalid
2
ns
td( i
td(pipe)
Pipeline delay (latency)
I data
5.5
5.5
5.5
CLK
cycles
Q data
6.5
6.5
6.5
td(a)
tj(a)
tdis
ten
tsu(O)
NOTE 7: Conversion rate is 1/2 the clock rate, fclk.
Aperture delay time
3
ns
Aperture jitter
1.5
ps, rms
Disable time, OE rising to Hi-Z
Enable time, OE falling to valid data
5
5
ns
ns
Output setup time from data to COUT or COUT
8
7
ns
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