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參數(shù)資料
| 型號： | THS0842PFB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT |
| 中文描述： | 雙輸入，8位，40 MSPS的低功耗模擬數(shù)字轉(zhuǎn)換器單路或雙路并行總線輸出 |
| 文件頁數(shù)： | 24/29頁 |
| 文件大?。?/td> | 479K |
| 代理商： | THS0842PFB |
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THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
dc coupled input
C
THS0842
+
–
CML
R
AIN+
R
R
R
VIN
AIN–
REFT
REFB
C
THS0842
CML
AIN–
VIN
AIN+
REFT
REFB
Figure 24. DC-Coupled Input Circuits
For dc-coupled systems, an op-amp can level shift a ground referenced input signal. A circuit like Figure 27
could be used. In this case, the AIN voltage is given by: AIN = –V
IN
+ V
CML
reference terminals
The THS0842 input voltage range is determined by the voltages on terminals REFBI and REFTI. Since the
device has an internal voltage reference generator, it must be placed in power down before applying an external
voltage to the REFT and REFB pins. Especially at higher sampling rates, it is advantageous to have a wider
analog input range. This can be achievable by using external voltage references (e.g., at AV
DD
= 3.3 V, the full
scale range can be extended from 1 V
pp
(internal reference) to 1.3 V
pp
(external reference) as shown in Table 1).
These voltages should not be derived via a voltage divider from a power supply source. Instead, use a
bandgap-derived voltage reference to derive both references via an op-amp circuit. Refer to the schematic of
the THS0842 evaluation module in this datasheet for an example circuit.
When using external references, the full-scale ADC input range and its dc position can be adjusted. The
full-scale ADC range is always equal to V
REFT
– V
REFB
. The maximum full-scale range is dependent on AV
DD
as shown in the specification section. Next to the constraint on their difference, there are limitations on the useful
range of V
REFT
and V
REFB
individually as well, dependent also on AV
DD
.
Table 1 summarizes these limits for 3 cases.
Table 1. Min/Max Reference Input Levels
AVDD
3 V
VREFB(min)
0.8 V
VREFB(max)
1.2 V
VREFT(min)
1.8 V
VREFT(max)
2.2 V
[VREFT–VREFB]max
1 V
3.3 V
0.8 V
1.2 V
2.1 V
2.5 V
1.3 V
3.6 V
0.8 V
1.2 V
2.4 V
2.8 V
1.6 V
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