參數(shù)資料
型號(hào)： THS0842PFB
廠商： Texas Instruments, Inc.
英文描述： DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
中文描述： 雙輸入，8位，40 MSPS的低功耗模擬數(shù)字轉(zhuǎn)換器單路或雙路并行總線輸出
文件頁(yè)數(shù)： 25/29頁(yè)
文件大?。?/td> 479K
代理商： THS0842PFB
THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
digital inputs
The digital inputs are CLK, STDBY, PWDN_REF, and OE. All these signals, except CLK, have an internal
pulldown resistor to connect to digital ground. This provides a default active operation mode using internal
references when left unconnected.
The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be
minimized by proper termination of the signal close to the THS0842. An important cause of performance
degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the
ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by
its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2
N
) of a signal
that needs to be sampled and the maximum amount of aperture error dt
max
that is tolerable. The following
formula shows the relation:
dtmax
1
f 2N
1
As an example, for an 8-bit converter with a 15-MHz input, the jitter needs to be kept <41 pS in order not to have
changes in the LSB of the ADC output due to the total aperture error.
digital outputs
The output of THS0842 is straight binary code. Capacitive loading on the output should be kept as low as
possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading
causes higher dynamic output currents and can increase noise coupling into the device analog front end. To
drive higher loads, use an output buffer is recommended. See Figure 25 through Figure 28 for examples.
When clocking output data from the THS0842, it is important to observe its timing relation to CLK. Pipeline ADC
delay is 55 clock cycles to which the maximum output propagation delay is added. See Note 6 in the specification
section for more details.
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