參數(shù)資料
型號(hào)： THS0842PFB
廠商： Texas Instruments, Inc.
英文描述： DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
中文描述： 雙輸入，8位，40 MSPS的低功耗模擬數(shù)字轉(zhuǎn)換器單路或雙路并行總線輸出
文件頁(yè)數(shù)： 4/29頁(yè)
文件大?。?/td> 479K
代理商： THS0842PFB
THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AVDD
AVSS
NO.
27, 37, 41
I
Analog supply voltage
28, 36, 40,
46
I
Analog ground
BG
29
O
Band gap reference voltage. A 1-
μ
F capacitor with a 0.1-
μ
F capacitor in parallel should be connected
between this terminal and AVSS for external filtering.
Clock input. The input is sampled on each rising edge of CLK.
Common mode level. This voltage is equal to (AVDD – AVSS)/2. An external 1-
μ
F capacitor with a 0.1-
μ
F
capacitor in parallel should be connected between this terminal and AVSS.
Latch clock for the data outputs
CLK
47
I
CML
32
O
COUT
COUT
DB7 – DB0
26
O
25
O
Inverted latch clock for the data outputs
4 – 11
O
Data outputs. D7 is the MSB. This is the second bus. Data is output from the Q channel when dual bus
output mode is selected. Pin SELB selects the output mode.
DRVDD
DRVSS
DA7 – DA0
1, 13
I
Supply voltage for output drivers
12, 24
I
Ground for digital output drivers
16 – 23
I
Data outputs for bus A. D7 is MSB. This is the primary bus. Data from both input channels can be output
on this bus or data from the I channel only. Pin SELB selects the output mode.
DVDD
DVSS
I–
45
I
Digital supply voltage
43
I
Digital ground
39
I
Negative input for analog channel 0.
I+
38
I
Positive input for analog channel 0.
NC
2,3,14,15
No connect. Reserved for future use
OE
48
I
Output enable. A high on this terminal will disable the output bus.
PWDN_REF
33
I
Power down for internal reference voltages. A high on this terminal will disable the internal reference
circuit.
Q–
35
I
Negative input for analog channel 1
Q+
34
I
Positive input for analog channel 1
REFB
30
I/O
Reference voltage bottom. The voltage at this terminal defines the bottom reference voltage for the ADC.
Sufficient filtering should be applied to this input. A 1-
μ
F capacitor with a 0.1-
μ
F capacitor in parallel should
be connected between REFB and AVSS. Additionally, a 0.1-
μ
F capacitor can be connected between REFT
and REFB.
REFT
31
I/O
Reference voltage top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient
filtering should be applied to this input. A 1-
μ
F capacitor with a 0.1-
μ
F capacitor in parallel should be
connected between REFT and AVSS. Additionally, a 0.1-
μ
F capacitor can be connected between REFT
and REFB.
SELB
44
I
Selects either single bus or data output or dual bus output data output. A low selects dual bus data output.
STBY
42
I
Standby input. A high level on this terminal will power down the device.
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