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| 型號： | TFP513PAPG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TI PANELBUS DIGITAL TRANSMITTER |
| 中文描述： | 德州儀器PANELBUS數(shù)字發(fā)射機 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大小： | 424K |
| 代理商： | TFP513PAPG4 |
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SLLS611 AUGUST 2004
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I
2
C interface
The I
2
C interface is used to access the internal registers. This two-pin interface consists of the SCL clock line
and the SDA serial data line. The basic I
2
C access cycles are shown in Figure 10 and Figure 11.
Start Condition (S)
Stop Condition (P)
SDA
SCL
Figure 10. I
2
C Start and Stop Conditions
The basic access write cycle consists of the following:
1.
2.
3.
4.
5.
A start condition
A slave address cycle
A subaddress cycle
Any number of data cycles
A stop condition
The basic access read cycle consists of the following:
1.
2.
3.
4.
5.
6.
7.
A start condition
A slave write address cycle
A subaddress cycle
A restart condition
A slave read address cycle
Any number of data cycles
A stop condition
The start and stop conditions are shown in Figure 10. The high-to-low transition of SDA while SCL is high defines
the start condition. The low-to-high transition of SDA while SCL is high defines the stop condition. Each cycle,
data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving
device. Thus, each data/address cycle contains 9 bits as shown in Figure 11.
SCL
1
2
3
4
5
6
7
8
9
SDA
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
1
Slave Address
Subaddress
Data
Stop
8
9
Figure 11. I
2
C Access Cycles
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