參數(shù)資料
型號(hào)： TFP513PAPG4
廠商： Texas Instruments, Inc.
英文描述： TI PANELBUS DIGITAL TRANSMITTER
中文描述： 德州儀器PANELBUS數(shù)字發(fā)射機(jī)
文件頁(yè)數(shù)： 19/29頁(yè)
文件大?。?/td> 424K
代理商： TFP513PAPG4
SLLS611 AUGUST 2004
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register descriptions (continued)
REV_ID
Subaddress = 04
Read Only
Default = 0x00
7
6
5
4
3
2
1
0
REV_ID[7:0]
This read-only register contains the revision ID.
RESERVED
Subaddress = 0705
Read Only
Default = 0x641400
7
6
5
4
3
2
1
0
Reserved
CTL_1_MODE
Subaddress = 08
Read/Write
Default = 0xBE
7
6
5
4
3
2
1
0
RSVD
TDIS
VEN
HEN
DSEL
BSEL
EDGE
PD
PD: This read/write register contains the power-down mode.
0: Power down (default after RESET)
1: Normal operation
EDGE: This read/write register contains the edge select mode.
0: Input data latches to the falling edge of IDCK+.
1: Input data latches to the rising edge of IDCK+.
BSEL: This read/write register contains the input bus select mode.
0: 12-bit operation with dual-edge clock
1: 24-bit operation with single-edge clock
DSEL:This read/write register is used in combination with BSEL and VREF to select the single-ended or differential
input clock mode. In the high-swing mode, DSEL is a don’t care because IDCK is always single-ended.
HEN: This read/write register contains the horizontal sync enable mode.
0: HSYNC input is transmitted as a fixed low.
1: HSYNC input is transmitted in its original state.
VEN: This read/write register contains the vertical sync enable mode.
0: VSYNC input is transmitted as a fixed low.
1: VSYNC input is transmitted in its original state.
TDIS: This read/write register contains the T.M.D.S. disable mode.
0: T.M.D.S. circuitry enable state is determined by PD.
1: T.M.D.S. circuitry is disabled.
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