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參數(shù)資料
| 型號： | TFP513PAP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TI PANELBUS DIGITAL TRANSMITTER |
| 中文描述： | 德州儀器PANELBUS數(shù)字發(fā)射機 |
| 文件頁數(shù)： | 4/29頁 |
| 文件大?。?/td> | 424K |
| 代理商： | TFP513PAP |
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SLLS611 AUGUST 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NUMBER
Input Pins (Continued)
DK3
6
I
This input pin is not used for the TFP513. It contains a weak pulldown resistor and may be left
unconnected. If a pullup resistor is connected to VDD, it must be in the range of 900
to 5 k
.
Horizontal sync input
HSYNC
4
I
IDCK
IDCK+
56
57
I
Differential clock input. The TFP513 supports both single-ended and fully differential clock input modes.
In the single-ended clock input mode, the IDCK+ input (pin 57) must be connected to the single-ended
clock source and the IDCK input (pin 56) must be tied to GND. In the differential clock input mode, the
TFP513 uses the crossover point between the IDCK+ and IDCK signals as the timing reference for
latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. The differential clock input mode is only
available in the low-signal-swing mode.
VSYNC
5
I
Vertical sync input
Configuration/Programming Pins
BSEL/SCL
15
I/O
Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is
enabled or disabled. This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), a high level selects the 24-bit input, single-edge input mode. A low
level selects the 12-bit input, dual-edge input mode.
When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C
register
descriptions
section). In this configuration, this pin has an open-drain output that requires an external
5-k
pullup resistor connected to VDD.
DSEL / I2C data. The operation of this pin depends on whether the I2C interface is enabled or disabled.
This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), this pin is used with BSEL and VREF to select the single-ended or
differential input clock mode (see the
universal graphics controller interface modes
section).
When I2C is enabled (ISEL = high), this pin functions as the I2C bidirectional data line. In this
configuration, this pin has an open-drain output that requires an external 5-k
pullup resistor connected
to VDD.
Edge select / hot plug input. The operation of this pin depends on whether the I2C interface is enabled or
disabled. This input is 3.3-V tolerant only.
When I2C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of the
input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock
IDCK+. This is the case for both single-ended and differential input clock modes.
When I2C is enabled (ISEL = high), this pin monitors the hot plug detect signal (see the DVI or VESA
P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-k
resistor.
I2C interface select / I2C RESET (active low, asynchronous).
If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C
register descriptions
section.
If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins
(BSEL, DSEL, EDGE, VREF) and state pin (PD).
If ISEL is brought low and then back high, the I2C state machine is reset. The register values are
changed to their default values and are not preserved from before the reset.
Monitor sense / programmable output 1. The operation of this pin depends on whether the I2C interface
is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-k
pullup resistor connected to VDD is required on this pin.
When I2C is disabled (ISEL = low), a high level indicates a powered-on receiver is detected at the
differential outputs. A low level indicates a powered-on receiver is not detected. This function is valid
only in dc-coupled systems.
When I2C is enabled (ISEL = high), this output is programmable through the I2C interface (see the I2C
register descriptions
).
DSEL/SDA
14
I/O
EDGE/HTPLG
9
I
ISEL/RST
13
I
MSEN
11
O
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