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參數(shù)資料
| 型號： | TFP513PAP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TI PANELBUS DIGITAL TRANSMITTER |
| 中文描述： | 德州儀器PANELBUS數(shù)字發(fā)射機 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 424K |
| 代理商： | TFP513PAP |
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SLLS611 AUGUST 2004
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register descriptions (continued)
CTL_2_MODE
7
VLOW
Subaddress = 09
5
MSEL[3:1]
Read/Write
Default = 0x00
6
4
3
2
1
0
TSEL
RSEN
HTPLG
MDI
MDI: This read/write register contains the monitor detect interrupt mode.
0: Detected logic level change in detection signal (to clear, write 1 to this bit).
1: Logic level remains the same.
HTPLG: This read-only register contains the hot plug detection input logic state.
0: Low level detected on the EDGE/HTPLG pin (pin 9).
1: High level detected on the EDGE/HTPLG pin (pin 9).
RSEN: This read only register contains the receiver sense input logic state, which is valid only for dc-coupled systems.
0: A powered-on receiver is not detected.
1: A powered-on receiver is detected (that is, connected to the DVI transmitter outputs).
TSEL: This read/write register contains the interrupt generation source select.
0: Interrupt bit (MDI) is generated by monitoring RSEN.
1: Interrupt bit (MDI) is generated by monitoring HTPLG.
MSEL[3:1]: This read/write register contains the source select of the monitor sense output pin.
000: Disabled. MSEN output high.
001: Outputs the MDI bit (interrupt).
010: Outputs the RSEN bit (receiver detect).
011: Outputs the HTPLG bit (hot plug detect).
VLOW: This read-only register indicates the V
REF
input level.
0: This bit is a logic level 0 if the V
REF
analog input selects high-swing inputs.
1: This bit is a logic level 1 if the V
REF
analog input selects low-swing inputs.
CTL_3_MODE
Subaddress = 0A
Read/Write
Default = 0x80
7
6
5
4
3
2
1
0
DK[3:1]
DKEN
RSVD
CTL[2:1]
RSVD
CTL[2:1]:This read/write register contains the values of the two CTL[2:1] bits that are output on the DVI port during
the blanking interval. CTL[3] is not available on the TFP513 because it is internally generated by the HDCP
circuitry.
DKEN: This read/write register controls the data de-skew enable.
0: Data de-skew is disabled; the values in DK[3:1] are not used.
1: Data de-skew is enabled; the de-skew setting is controlled through DK[3:1].
DK[3:1]: This read/write register contains the de-skew setting, each increment adjusts the skew by t
(STEP)
.
000: Step 1 (minimum setup/maximum hold)
001: Step 2
010: Step 3
011: Step 4
100: Step 5 (default)
101: Step 6
110: Step 7
111: Step 8 (maximum setup/minimum hold)
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