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參數(shù)資料
| 型號： | TFP513PAP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TI PANELBUS DIGITAL TRANSMITTER |
| 中文描述： | 德州儀器PANELBUS數(shù)字發(fā)射機 |
| 文件頁數(shù)： | 21/29頁 |
| 文件大小： | 424K |
| 代理商： | TFP513PAP |
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SLLS611 AUGUST 2004
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register descriptions (continued)
CFG
Subaddress = 0B
Read Only
7
6
5
4
3
2
1
0
CFG[7:0] (D[23:16])
This read-only register contains the state of the inputs D[23:16]. These pins can provide the user with selectable
configuration data through the I
2
C bus.
RESERVED
Subaddress = 0E0C
Read/Write
Default = 0x97D0A9
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
These read/write registers have no effect on TFP513 operation.
DE_DLY
Subaddress = 32
Read/Write
Default = 0x00
7
6
5
4
3
2
1
0
DE_DLY[7:0]
This read/write register defines the number of pixels after HSYNC goes active that DE is generated, when the DE
generator is enabled. The value must be less than or equal to (2047 DE_CNT).
DE_CTL
Subaddress = 33
Read/Write
Default = 0x00
7
6
5
4
3
2
1
0
Reserved
DE_GEN
VS_POL
HS_POL
Reserved
DE_DLY[8]
DE_DLY[8]: This read/write register contains the top bit of DE_DLY.
HS_POL: This read/write register sets the HSYNC polarity.
0: HSYNC is considered active low.
1: HSYNC is considered active high.
Pixel counts are reset on the HSYNC active edge.
VS_POL: This read/write register sets the VSYNC polarity.
0: VSYNC is considered active low.
1: VSYNC is considered active high.
Line counts are reset on the VSYNC active edge.
DE_GEN: This read/write register enables the internal DE generator.
0: DE generator is disabled. Signal required on DE pin
1: DE generator is enabled. DE pin is ignored.
DE_TOP
Subaddress = 34
Read/Write
Default = 0x00
7
6
5
4
3
2
1
0
DE_TOP[7:0]
This read/write register defines the number of pixels after VSYNC goes active that DE is generated, when the DE
generator is enabled.
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