參數(shù)資料
型號: TFDU8108
廠商: Vishay Intertechnology,Inc.
英文描述: Very Fast IrDA in Standard package
中文描述: 非??焖俚腎rDA標(biāo)準(zhǔn)包裝
文件頁數(shù): 21/27頁
文件大小: 820K
代理商: TFDU8108
TFDU8108
Vishay Semiconductors
Document Number 82558
Rev. 1.6, 12-Aug-04
www.vishay.com
21
Appendix C
Serial Interface (SIF) Programming Guide
The SIF port of this module allow an IR controller to
communicate with it, get module ID and capability
information, implement receiver bandwidth mode
switching, LED power control, shutdown and some
other functions.
This interface requires three signals: a clock line
(SCLK) that is used for timing, and two unidirectional
lines multiplexed with the transmitter (Txd, write) and
receiver (Rxd, read) infrared signal lines.
The supported programming sequence formats are
listed below:
one-byte special commands
two-byte write commands
two-byte read commands
three-byte read commands
The one-byte special command sequences are
reserved for time-critical actions, while the two-byte
write command is predominantly used to set basic
transceiver characteristics. More information can be
found in the IrDA document "Serial Interface for
Transceiver Control, v 1.0a" on IrDA.org web site.
Serial Interface Timing Specifications
In general, serial interface programming sequences
are similar to any clocked-data protocol:
there is a range of acceptable clock rates, mea-
sured from rising edge to rising edge
there is a minimum data setup time before clock ris-
ing edges
there is a minimum data hold time after clock rising
edges
Recommended programming timing:
(4 kHz <) fclk < 8 MHz (4 kHz is a recommended
value, according to the Serial Interface Standard
quasi-static programming is possible)
TCLK > 125 ns (< 250
μ
s, see the remark for quasi-
static programming above)
Tsetup > 10 ns
Thold > 10 ns
The timing diagrams below show the setup and hold
time for Serial Interface programming sequences:
Protocol Specifications
The serial interface protocol is a command-based
communication standard and allows for the communi-
cation between controller and transceiver by way of
serial programming sequences on the clock (SCLK),
transmit (TX), and receive (RX) lines. The SCLK line
is used as a clocking signal and the transmit/receive
lines are used to write/read data information. The pro-
tocol requires all transceivers to implement the write
commands, but does not require the read-portion of
the protocol to be implemented (though all transceiv-
ers must at least follow the various commands, even
if they perform no internal action as a result). This
serial interface follows but does not support all read/
write commands or extended commands, supporting
only the special commands and basic write/read com-
mands.
Write commands to the transceiver take place on the
SCLK and TX lines and may make use of the RX line
for answer back purposes.
A command may be directed to a single transceiver
on the SCLK, TX and RX bus by specifying a unique
three-bit transceiver address, or a command may be
directed to all transceivers on the bus by way of a spe-
cial three-bit broadcast address code. The Vishay
VFIR transceiver TFDU8108 will respond to trans-
ceiver address 010 and the broadcast address 111
only, and follows but ignores all other transceiver
addresses. The transceiver address of Vishay FIR
module TFDU6108 is 001.
All commands have a common \"header\" or series of
leading bits which take the form shown below.
SCLK
TX
125 ns < Tclk
s
Tsetup > 10 ns
Thold > 10 ns
18496
0
1
1/0 R0 R1 R2 R3 A0 A1 A2
...
Sync
Bits
Register
Address
Transceiver
Address
1=Write
0=Read
first bit sent to
transceiver
last bit sent to
transceiver
18497
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