參數(shù)資料
型號(hào): TFDU8108
廠商: Vishay Intertechnology,Inc.
英文描述: Very Fast IrDA in Standard package
中文描述: 非常快速的IrDA標(biāo)準(zhǔn)包裝
文件頁(yè)數(shù): 18/27頁(yè)
文件大?。?/td> 820K
代理商: TFDU8108
www.vishay.com
18
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Registers Data Depth
In general the whole data registers consist of a data
depth of eight bits. But sometimes it is unnecessary to
implement the full depth. In such a case the invisible
bits consider like a zero.
Used Index Commands
The table shows the valid index commands, its allowable modes, and the data depth to them.
Commands INDEX
[3:0]
0h
W/R
1h
W/R
2h
W/R
Bh - 3h
X
Ch
X
Dh
W
Note: The main_ctrl_1 register is written software dependent on the offset value stored in ext_ctrl_7 and ext_ctrl_8 registers.
The main_ctrl_1 register can be set to the following values, shown in the table.
Main-ctrl-0 register values
1)
APEN - Acknowledge Pulse Enable, (optional)
This bit is used to enable the acknowledge pulse. When it is set to 1 and RX OEN is 1 (receiver output enabled) the IRRX/SRDAT line will
be pulsed low for one clock cycle upon successful completion of every write command or special command with individual (non broadcast)
transceiver address. The internal signal from the receiver photo diode is disconnected when this bit is set to 1.
Mode
Actions
Register Name
Data Bits
TFDU8108
default
00h
00h
70h
Common control
Infrared mode
Txd power level
Not used
Not used
Reset transceiver,
Only one byte!
Not used
Not used
Not used
Extended indexing
main-ctrl-0 register
main-ctrl-1 register
main-ctrl-2 register
[4:0]
[7:0]
[7:4]
R
X
W
R
Eh
Fh
Value
bit 0
Function
Default
sleep
PM SL - Power Mode Select
0 > low power mode (sleep mode)
1 > normal operation power mode
RX OEN - Receiver Output Enable
0 > IRRX/SRDAT line disable (tri-stated)
1 > IRRX/SRDAT line enabled
TLED EN - Transmitter LED Enable
0 > disabled
1 > enabled
not used
APEN
1)
bit 1
disable
bit 2
disable
bit 3
bit 4
not used
disable
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