參數(shù)資料
型號(hào): TFDU8108
廠商: Vishay Intertechnology,Inc.
英文描述: Very Fast IrDA in Standard package
中文描述: 非常快速的IrDA標(biāo)準(zhǔn)包裝
文件頁(yè)數(shù): 16/27頁(yè)
文件大?。?/td> 820K
代理商: TFDU8108
www.vishay.com
16
Document Number 82558
Rev. 1.6, 12-Aug-04
TFDU8108
Vishay Semiconductors
Switching Characteristics
Maximum capacitive load = 20 pF
*)
Parameters
SCLK Clock Period
SCLK Clock High Time
SCLK Clock Low Time
Output Data Valid
(from infrared controller)
Output Data Hold
(from infrared controller)
Output Data Valid
(from optical transceiver)
Output Data Hold
(from optical transceiver)
Line Float Delay
Input Data Setup
Input Data Hold
*)
Capacitive load is different from "Serial interface - specification". For the bus protocol see
"RECOMMENDED SERIAL INTERFACE FOR
TRANSCEIVER CONTROL, Draft Version 1.0a, March 29, 2000, IrDA"
. In Appendix B the transceiver related data are given.
Test Conditions
Symbol
tCKp
tCKh
tCKl
tDOtv
Min.
250
60
80
Max.
infinity
Unit
ns
ns
ns
ns
R.E., SCLK to next R.E., SCLK
At 2.0 V for single-ended signals
At 0.8 V for single-ended signals
After F.E., SCLK
40
After F.E., SCLK
tDOth
0
ns
After R.E., SCLK
tDOrv
40
ns
After R.E., SCLK
tDOrh
40
ns
After R.E., SCLK
Before R.E., SCLK
After R.E., SCLK
tDOrf
tDIs
tDIh
60
ns
ns
ns
10
5
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