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參數(shù)資料
| 型號： | TF28F008SA-100 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
| 中文描述： | 1M X 8 FLASH 12V PROM, 100 ns, PDSO40 |
| 封裝： | 10 X 20 MM, REVERSE, TSOP-40 |
| 文件頁數(shù)： | 2/33頁 |
| 文件大?。?/td> | 466K |
| 代理商： | TF28F008SA-100 |
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28F008SA
PRODUCT OVERVIEW
The
(8,388,608 bit) memory organized as
1 Mbyte
(1,048,576 bytes) of 8 bits each.
Sixteen 64-Kbyte
(65,536 byte)
blocks
are included on the 28F008SA.
A memory map is shown in Figure 6 of this specifica-
tion. A block erase operation erases one of the six-
teen blocks of memory in typically
1.6 seconds
, in-
dependent of the remaining blocks. Each block can
be independently erased and written
100,000 cy-
cles
.
Erase Suspend
mode allows system software
to suspend block erase to read data or execute
code from any other block of the 28F008SA.
28F008SA
is
a
high-performance
8-Mbit
The 28F008SA is available in the
40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-
lead PSOP
(Plastic Small Outline) packages. Pin-
outs are shown in Figures 2 and 4 of this specifica-
tion.
The
Command User Interface
serves as the inter-
face between the microprocessor or microcontroller
and the internal operation of the 28F008SA.
Byte Write and Block Erase Automation
allow
byte write and block erase operations to be execut-
ed using a two-write command sequence to the
Command User Interface. The internal
Write State
Machine
(WSM) automatically executes the algo-
rithms and timings necessary for byte write and
block
erase
operations,
thereby unburdening the microprocessor or micro-
controller. Writing of memory data is performed in
byte increments typically within
9
m
s
, an 80% im-
provement over current flash memory products.
I
PP
byte write and block erase currents
are
10 mA
typical, 30 mA maximum. V
PP
byte write and
block erase voltage
is
11.4V to 12.6V
.
including
verifications,
The
Status Register
indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation.
The
RY/BY
Y
output gives an additional indicator of
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase,
for example). Status polling using RY/BY
Y
mini-
mizes both CPU overhead and system power con-
sumption. When low, RY/BY
Y
indicates that the
WSM is performing a block erase or byte write oper-
ation. RY/BY
Y
high indicates that the WSM is ready
for new commands, block erase is suspended or the
device is in deep powerdown mode.
Maximum access time is
85 ns (t
ACC
)
over the com-
mercial temperature range (0
§
C to
70
§
C) and over
V
CC
supply voltage range (4.5V to 5.5V and 4.75V to
5.25V).
I
CC
active current
(CMOS Read) is
20 mA
typical, 35 mA maximum at 8 MHz
.
When the CE
Y
and RP
Y
pins are at V
CC
, the
I
CC
CMOS Standby
mode is enabled.
A
Deep Powerdown
mode is enabled when the
RP
Y
pin is at GND, minimizing power consumption
and providing write protection.
I
CC
current
in deep
powerdown is
0.20
m
A typical
. Reset time of 400 ns
is required from RP
Y
switching high until outputs are
valid to read attempts. Equivalently, the device has a
wake time of 1
m
s from RP
Y
high until writes to the
Command User Interface are recognized by the
28F008SA. With RP
Y
at GND, the WSM is reset
and the Status Register is cleared.
2
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