TEA1612T_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 24 September 2009
9 of 19
NXP Semiconductors
TEA1612T
Zero voltage switching resonant converter controller
At start-up the soft start capacitor is charged to VVCO(start) setting a start-up frequency of
about 80 % of the maximum frequency. After start-up the external soft start capacitor is
discharged by Istart(soft). The VCO pin voltage follows the CSS voltage (discharging takes
place via Rf) and the frequency sweeps down. The CSS capacitor determines the
frequency sweep rate.
When the circuit comes into regulation, the error amplier output controls the VCO pin
voltage and the CSS voltage sweeps down further to zero volt.
7.8 VAUX input
The TEA1612T can start up either via a start-up bleeder resistor (connected to the high
voltage and VDD) or via the VAUX input. In the latter case the internal 10 k resistor (from
VAUX to VDD) initiates charging of the VDD capacitor after which the series regulator takes
over. The series regulator is active up to the moment that VDD equals VDD(reg). Further
charging to VDD(startup) is done via the internal 10 k resistor.
In oscillation state the start-up resistor is no longer capable of delivering the VDD supply
current, so an auxiliary supply (for instance, via an auxiliary winding or a dV/dt supply)
needs to take over. The VAUX input facilitates a series regulator which regulates its output
voltage (= VDD) to VDD(reg).
7.9 Burst mode
In the application the amount of converted power can be estimated from the actual
operating frequency: the higher the frequency, the lower the output power. This frequency
is proportional to the feedback current to the IRS pin which is measured via a sense
resistor Rfb2 (see Figure 7). The actual feedback current equals 1/Rfb2 × (VBURST VIRS). When the voltage at the BURST pin exceeds Vref(BURST), the TEA1612T output drivers
(GL, GH) are made inactive (i.e. low). The output drivers are enabled again when the
voltage at the BURST pin falls below the preset voltage at the HYST pin.
7.10 Shut-down
The shut-down input on pin SD has an accurate threshold level of 2.33 V. When the
voltage on input SD reaches 2.33 V, the TEA1612T enters shut-down mode.
During shut-down mode, VDD is clamped by an internal Zener diode at 12.0 V with 1 mA
input current. This clamp prevents VDD rising above the rating of 14 V due to low supply
current to the TEA1612T in shut-down mode.
When the TEA1612T is in shut-down mode, it can only be activated again by lowering VDD
to below the VDD(rst) level (typically 5.3 V) or by making the reset input active. The
shut-down latch is then reset and a new start-up cycle can commence.
In shut-down mode the GL pin is high and the GH pin is low. In this way the bootstrap
capacitor remains charged so that after a reset a new cycle can start well dened.
7.11 Latch reset input
The internal shut-down latch can be reset via the reset input.This input is active low.