參數(shù)資料
型號: TE28F160B3BC70
廠商: INTEL CORP
元件分類: DRAM
英文描述: 3 Volt Advanced Boot Block Flash Memory
中文描述: 1M X 16 FLASH 2.7V PROM, 70 ns, PDSO48
封裝: 12 X 20 MM, TSOP-48
文件頁數(shù): 5/49頁
文件大?。?/td> 427K
代理商: TE28F160B3BC70
E
1.0
SMART 3 ADVANCED BOOT BLOCK
–WORD-WIDE
5
PRELIMINARY
INTRODUCTION
This
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V
–2.2V or 2.7V–3.6V I/Os and a low V
CC
/V
PP
operating range of 2.7V–3.6V for read and
program/erase operations. In addition this family is
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “V
PP
= 12V” refers to 12V ±5%.
Section 1 and 2 provides an overview of the flash
memory family including applications, pinouts and
pin descriptions. Section 3 describes the memory
organization and operation for these products.
Finally, Sections 4, 5, 6 and 7 contain the
operating specifications.
preliminary
datasheet
contains
the
1.1
Smart 3 Advanced Boot Block
Flash Memory Enhancements
The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3
Advanced Boot Block flash memory provides a
convenient upgrade from and/or compatibility to
previous 4-Mbit and 8-Mbit Boot Block products.
The Smart 3 product functions are similar to lower
density products in both command sets and
operation, providing similar pinouts to ease density
upgrades.
The Smart 3 Advanced Boot Block flash memory
features
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
Program Suspend command which permits
program suspend to read
WP# pin to lock and unlock the upper two (or
lower two, depending on location) 4-Kword
blocks
V
CCQ
input for 1.8V–2.2V on all I/Os. See
Figure 1-4 for pinout diagrams and V
CCQ
location
Maximum program time specification for
improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
28F160B3
Reference
V
CC
Read Voltage
2.7V– 3.6V
Table 9, Table 12
V
CCQ
I/O Voltage
1.8V–2.2V or 2.7V– 3.6V
Table 9, Table 12
V
PP
Program/Erase Voltage
2.7V– 3.6V or 11.4V– 12.6V
Table 9, Table 12
Bus Width
16 bit
Table 2
Speed
120 ns
Table 15
Memory Arrangement
256-Kbit x 16 (4-Mbit), 512-Kbit x 16 (8-Mbit),
1024-Kbit x 16 (16-Mbit)
Blocking (top or bottom)
Eight 4-Kword parameter blocks (4/8/16) &
Seven 32-Kword blocks (4-Mbit)
Fifteen 32-Kword blocks (8-Mbit)
Thirty-one 32-Kword main blocks (16-Mbit)
Section 2.2
Figures 5 and 6
Locking
WP# locks/unlocks parameter blocks
All other blocks protected using V
PP
switch
Section 3.3
Table 8
Operating Temperature
Extended: –40
°
C to +85
°
C
Table 9, Table 12
Program/Erase Cycling
10,000 cycles
Table 9, Table 12
Packages
48-Lead TSOP, 48-Ball
μ
BGA* CSP
Figures 1, 2, 3,
and 4
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