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參數(shù)資料
| 型號： | TE28F016C3T90 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 中文描述： | 3伏高級啟動(dòng)塊8 - ，16 - ，32 - Mbit閃存家庭 |
| 文件頁數(shù)： | 15/59頁 |
| 文件大?。?/td> | 384K |
| 代理商： | TE28F016C3T90 |
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E
3.2.6.1
3 VOLT ADVANCED+ BOOT BLOCK
15
PRODUCT PREVIEW
Suspending and Resuming Erase
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in
order to read data from or program data to another
block in memory. Once the erase sequence is
started, writing the Erase Suspend command to the
CUI
suspends
the
erase
predetermined point in the erase algorithm. The
status register will indicate if/when the erase
operation has been suspended. Erase suspend
latency is specified by t
WHRH2
/t
EHRH2
.
sequence
at
a
A Read Array/Program command can now be
written to the CUI to read/program data from/to
blocks other than that which is suspended. This
nested Program command can subsequently be
suspended to read yet another location. The only
valid commands while erase is suspended are
Read Status Register, Read Configuration, Read
Query, Program Setup, Program Resume, Erase
Resume, Lock Block, Unlock Block and Lock-Down
Block. During erase suspend mode, the chip can be
placed in a pseudo-standby mode by taking CE# to
V
IH
. This reduces active current consumption.
Erase Resume continues the erase sequence when
CE# = V
IL
. As with the end of a standard erase
operation, the status register must be read and
cleared before the next instruction is issued.
Table 5. Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Command
Notes
Oper
Addr
Data
Oper
Addr
Data
Read Array
4
Write
X
FFH
Read Configuration
2, 4
Write
X
90H
Read
IA
ID
Read Query
2, 4
Write
X
98H
Read
QA
QD
Read Status Register
4
Write
X
70H
Read
X
SRD
Clear Status Register
4
Write
X
50H
Program
3,4
Write
X
40H/10H
Write
PA
PD
Block Erase/Confirm
4
Write
X
20H
Write
BA
D0H
Program/Erase Suspend
4
Write
X
B0H
Program/Erase Resume
4
Write
X
D0H
Lock Block
4
Write
X
60H
Write
BA
01H
Unlock Block
4
Write
X
60H
Write
BA
D0H
Lock-Down Block
4
Write
X
60H
Write
BA
2FH
Protection Program
4
Write
X
C0H
Write
PA
PD
X =
Don’t Care
SRD = Status Reg. Data
NOTES:
1.
Bus operations are defined in Table 3.
2.
Following the Read Configuration or Read Query commands, read operations output device configuration or CFI query
information, respectively. See Section 3.2.2 and 3.2.4.
3.
Either 40H or 10H command is valid, but the Intel standard is 40H.
4.
When writing commands, the upper data bus [DQ
8
–DQ
15
] should be either V
IL
or V
IH
, to minimize current draw.
PA = Prog Addr
PD = Prog Data
BA = Block Addr
IA
=
Identifier Addr.
ID = Identifier Data
QA = Query Addr.
QD = Query Data
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