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參數(shù)資料
| 型號： | TDA9923AHW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 4-CH 12-BIT RESISTANCE LADDER ADC, SERIAL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, 1.00 MM HEIGHT, PLASTIC, MS-026, SOT545-3, QFP-48 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 118K |
| 代理商： | TDA9923AHW |
9397 750 14207
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 6 February 2006
13 of 20
Philips Semiconductors
TDA9923A
Quad 12-bit, up to 40 Msample/s analog-to-digital converter
[1]
Block address selects the function to control. In a normal application, only the output phases can be
controlled.
[2]
Sub address selects the phase to control. In a normal application, only the output phases can be controlled.
[3]
Bit HW selects either the hardwired default settings or the serial control word.
[4]
W[0] is the LSB; W[6] is the MSB; see Figure 5
[5]
The default settings are:
a) Controlled phase for channel 1 output data (DAT1): W[6:0] = 000 0000.
b) Controlled phase for channel 2 output data (DAT2): W[6:0] = 000 0000.
c) Controlled phase for channel 3 output data (DAT3): W[6:0] = 000 0000.
d) Controlled phase for channel 4 output data (DAT4): W[6:0] = 000 0000.
e) Controlled phase for output strobe signal (DST): W[6:0] = 000 0000.
f) Controlled phase for output clock signal (DCLK): W[6:0] = 000 0011.
Table 7:
Serial interface programming
Block address
bits B[2:0] [1]
Sub address
bits S[3:0] [2]
Bit
HW [3]
Data bits W[6:0] [4]
001
any address
1
the hardwired default settings are used; see Table note 5
0110
0
controlled phase for channel 1 output data (DAT1)
0111
0
controlled phase for channel 2 output data (DAT2)
1000
0
controlled phase for channel 3 output data (DAT3)
1001
0
controlled phase for channel 4 output data (DAT4)
1010
0
controlled phase for output strobe signal (DST)
1100
0
controlled phase for output clock signal (DCLK)
other
addresses
0
internally-controlled phases (not to be used in normal
applications)
Other
addresses
any address
X
test modes (not to be used in normal applications)
Table 8:
Standby selection
Pin STDBY
Data bits D[11:0]
ICCA +ICCD +ICCO
HIGH
logic 0
<tbd>
LOW
active
<tbd>
Table 9:
Binary output coding
VCCA = 3.3 V; VVRB = 1.15 V; VVRT = 2.15 V; Vi(CM) = 1.65 V.
Step
VVInP
VVInN
Binary output bits
IR
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
U/F
< 1.15
> 2.15
0
0000000000
0
1.15
2.15
1
0
0000000000
1
:
1
0
0000000001
:
::::::::::
4094
:
1
1111111110
4095
2.15
1.15
1
1111111111
O/F
> 2.15
< 1.15
0
1
1111111111
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