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參數(shù)資料
| 型號(hào)： | TDA9923AHW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 4-CH 12-BIT RESISTANCE LADDER ADC, SERIAL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, 1.00 MM HEIGHT, PLASTIC, MS-026, SOT545-3, QFP-48 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 118K |
| 代理商： | TDA9923AHW |
9397 750 14207
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 6 February 2006
9 of 20
Philips Semiconductors
TDA9923A
Quad 12-bit, up to 40 Msample/s analog-to-digital converter
[1]
A termination resistor must be added externally.
[2]
Vgpd represents the ground potential difference voltage. This is the voltage that results from current owing through the nite resistance
and the inductance between the receiver and the driver circuit ground voltages.
[3]
The analog bandwidth is dened as the maximum input sine wave frequency that can be applied to the device with a maximum 3 dB
reduction in the reconstructed output. No glitches greater than 2 LSB, or any signicant attenuation should be observed in the
reconstructed signal.
Digital outputs: pins DATn, DSTn and DCLKn; fCLK = 40 MHz; CL = 1 pF; RL = 50 ; see Figure 6 and Table note 10
fDCLK
clock frequency of serial
data
-7fCLK
-
MHz
δDCLK
DCLK duty factor
48
-
50.5
%
td(CLKI-DCLK)
static delay time between
CLKI rising edge and DCLK
rising edge
default settings;
see Table 7
[11] -
4.50
-
ns
tskew(DCLK)
absolute skew of DCLK
referenced to CLKI
400
-
+400
ps
tjit(DCLK)(rms)
1-sigma jitter of DCLK
(RMS value)
referenced to CLKI
-
30
ps
td(DCLK-DATn)
static delay between DCLK
rising edge and DATn[D0]
default settings;
see Table 7
[11] -
0.50
-
ns
tskew(DATn)
absolute skew of DATn
referenced to DCLK
150
-
+150
ps
tjit(DATn)(rms)
1-sigma jitter of DATn
(RMS value)
referenced to DCLK
-
45
ps
tsu(DATn)
DATn set-up time (3-sigma) referenced to DCLK
260
-
ps
th(DATn)
DATn hold time (3-sigma)
referenced to DCLK
970
-
ps
td(DCLK-DST)
static delay between DCLK
rising edge and DST rising
edge
default settings;
see Table 7
[11] -
0.60
-
ns
tskew(DST)
absolute skew of DST
referenced to DCLK
150
-
+150
ps
tjitter(DST)(rms)
1-sigma jitter of DST
(RMS value)
referenced to DCLK
-
25
ps
tsu(DST)
DST set-up time (3-sigma)
referenced to DCLK
375
-
ps
th(DST)
DST hold time (3-sigma)
referenced to DCLK
890
-
ps
tr(SLVS)
SLVS rise time
10 % to 90 % transition
280
-
350
ns
tf(SLVS)
SLVS fall time
10 % to 90 % transition
250
-
350
ps
tlatency
clock cycle latency
-
8
-
period
Serial interface: pins SST, SCLK and SDAT; see Figure 4
fmax
maximum clock frequency
25
-
MHz
δ
duty factor
45
-
55
%
tsu(SDAT)
serial data set-up time
8
-
ns
th(SDAT)
serial data hold time
8
-
ns
tsu(SSTL)
serial strobe LOW set-up
time
8-
-
ns
th(SSTL)
serial strobe HIGH hold
time
8-
-
ns
Table 6:
Characteristics…continued
VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 0.75 V to 0.85 V; Tamb =0 °Cto70 °C; Vi(FS)(p-p) = 2 V; typical values
measured at VCCA = 3.3 V, VCCD = 1.8 V, VCCO = 0.8 V and Tamb =25 °C; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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