參數(shù)資料
型號(hào)： TDA9923AHW
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 4-CH 12-BIT RESISTANCE LADDER ADC, SERIAL ACCESS, PQFP48
封裝： 7 X 7 MM, 1.00 MM HEIGHT, PLASTIC, MS-026, SOT545-3, QFP-48
文件頁(yè)數(shù)： 2/20頁(yè)
文件大?。?/td> 118K
代理商： TDA9923AHW
9397 750 14207
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 6 February 2006
10 of 20
Philips Semiconductors
TDA9923A
Quad 12-bit, up to 40 Msample/s analog-to-digital converter
[4]
The THD is obtained with the addition of the rst ve harmonics and the division of the fundamental harmonic referenced at 0 dB for a
full-scale sine wave input:
[5]
The signal-to-noise ratio is the ratio of the RMS value of the input signal to the RMS sum of all harmonics above the 5th harmonic and
noise up to half of the clock frequency (Nyquist frequency).
[6]
The ENOB is obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the
clock frequency (Nyquist frequency). Conversion to SINAD (signal-to-noise and distortion ratio) is given by
SINAD = ENOB
× 6.02 + 1.76 dB.
[7]
Intermodulation measured relative to either tone with analog input frequencies of 5 MHz to 5.02 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (
6 dB below full-scale for each input signal).
[8]
Crosstalk is dened as the coupling between two adjacent channels at 4.43 MHz and 3.9 MHz, the interfering channel being driven by a
full-scale signal at 3.9 MHz.
[9]
Clock input:
a) The sampling delay takes into account all the contributions such as the matching, temperature and supplies variations.
b) The sampling delay spread is only the contribution of the matching for given temperature and supplies. It is included in the maximum
and minimum sampling delay.
[10] Digital outputs:
a) td(signal1-signal2) is the static delay between signal1 rising edge and signal2 rising edge at typical conditions and default settings.
b) tskew(signal2) is the delay variation of signal2 (referenced to signal1) from the nominal value (td(signal1-signal2)) over temperature and
supplies.
c) tjitter(signal2) is the 1-sigma jitter of signal2 (referenced to signal1).
d) tsu(signal2) = td(signal1 signal2)typical tskew(signal2)max 3 × tjitter(signal2).
e) th(signal2) = δDCLK(min) × (1/fCLK) + td(signal1-signal2)typical tskew(signal2)min 3 × tjitter(signal2).
[11] When using the serial interface (see Table 7), the delay will be:
a) td(CLKI-DCLK) = td(CLKI-DCLK)typical + (WDCLK[6:0] 3) × step.
b) td(DCLKI-DATn) = td(DCLK-DATn)typical + (WDATn[6:0] WDCLK[6:0] + 3) × step.
c) td(DCLKI-DST) = td(DCLK-DST)typical + (WDST[6:0] WDCLK[6:0] + 3) × step.
d) The value of one step is: step = 1/(fCLK × 112).
THD
20
H
fund
H
2
H
3
2
H
4
2
H
5
2
H
6
2
++++
------------------------------------------------------------------------------
log
=
Fig 3.
Clock levels
001aaa201
Vi(th)(dif)(max)
0 V differential
CLKI
CLKIN
Vi(th)(dif)(min)
Vi(th)(dif)(max)
Vi(max)
Vix(max)
Vix(min)
Vi(min)
CLKI, CLKIN
Vi(th)(dif)(min)
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