參數(shù)資料
型號(hào)： TDA9887TS/V3
廠商： NXP SEMICONDUCTORS
元件分類： 接收器
英文描述： AM/FM, AUDIO/VIDEO DEMODULATOR, PDSO24
封裝： 5.30 MM, PLASTIC, MO-150, SOT-340-1, SSOP-24
文件頁數(shù)： 2/56頁
文件大小： 230K
代理商： TDA9887TS/V3
2002 Mar 05
10
Philips Semiconductors
Product specication
I2C-bus controlled multistandard alignment-free
IF-PLL demodulator with FM radio
TDA9887TS
8.5
VCO and divider
The VCO of the VIF-FPLL operates as an integrated low
radiation relaxation oscillator at double the picture carrier
frequency. The control voltage, required to tune the VCO
to actually double the picture carrier frequency, is
generated at the loop filter by the frequency phase
detector. The possible frequency range is 50 to 140 MHz
(typical value).
The oscillator frequency is divided-by-two for providing two
differential square wave signals with exactly 90 degrees
phase difference, independent of the frequency, for use in
the FPLL detectors, the video demodulator and the
intercarrier mixer.
8.6
AFC and digital acquisition help
Each relaxation oscillator of the VIF-PLL and FM-PLL
demodulator has a wide frequency range. To prevent false
locking of the PLLs and with respect to the catching range,
the digital acquisition help provides an individual control,
until the frequency of the VCO is within the preselected
standard dependent lock-in window of the PLL.
The in-window and out-window control at the FM-PLL is
additionally be used to mute the audio stage (if auto mute
is selected via the I2C-bus).
The principle working of the digital acquisition help is as
following. The PLL VCO output is connected to a down
counter which has a predefined start value (standard
dependent). The VCO frequency clocks the down counter
for a fixed gate time. Thereafter, the down counter stop
value is analysed. In case the stop value is higher (lower)
than the expected value range, the VCO frequency is
lower (higher) than the wanted lock-in window frequency
range. A positive (negative) control current is injected into
the PLL loop filter and consequently the VCO frequency
will be increased (decreased) and a new counting cycle
starts.
The gate time as well as the control logic of the acquisition
help circuit is dependent on the precision of the reference
signal at pin REF. Operation as crystal oscillator is
possible as well as connecting this input via a serial
capacitor to an external reference frequency e.g. the
tuning system oscillator.
The AFC signal is derived from the corresponding down
counter stop value after a counting cycle. The last four bits
are latched and can be read out via the I2C-bus
(see Table 7). Also the digital-to-analog converted value is
given as current at pin AFC.
8.7
Video demodulator and amplier
The video demodulator is realized by a multiplier which is
designed for low distortion and large bandwidth. The VIF
signal is multiplied with the ‘in phase’ signal of the VIF-PLL
VCO.
The demodulator output signal is fed into the video
preamplifier via a level shift stage with integrated low-pass
filter to achieve carrier harmonics attenuation.
The output signal of the preamplifier is fed to the VIF-AGC
detector (see Section 8.3) and in the sound trap mode also
fed internally to the integrated sound carrier trap
(see Section 8.8). The differential trap output signal is
converted and amplified by the following postamplifier.
The video output level at pin CVBS is 2 V (p-p).
In the bypass mode the output signal of the preamplifier is
fed directly through the postamplifier to pin CVBS. The
output video level is 1.1 V (p-p) for using an external sound
trap with 10% loss over all.
Noise clipping is provided in both cases.
8.8
Sound carrier trap
The sound carrier trap consists of a reference filter, a
phase detector and the sound trap itself.
A sound carrier reference signal is fed into the reference
low-pass filter and is shifted by nominal 90 degrees. The
phase detector compares the original reference signal with
the signal shifted by the reference filter and produces a
DC voltage by charging or discharging an integrated
capacitor with a current proportional to the phase
difference between both signals, respectively to the
frequency error of the integrated filters. The DC voltage
controls the frequency position of the reference filter and
the sound trap. So the accurate frequency position for the
different standards is set by the sound carrier reference
signal.
The sound trap itself is constructed of three separate traps
to realize sufficient suppression of the first and second
sound carrier.
8.9
SIF amplier
The SIF amplifier consists of three AC-coupled differential
stages. Gain control is performed by emitter degeneration.
The total gain control range is typical 66 dB. The
differential input impedance is typical 2 k
in parallel with
3 pF.
相關(guān)PDF資料
PDF描述
TDA9889TS/V1,512 SPECIALTY CONSUMER CIRCUIT, PDSO16
TDA9889TS/V1,518 SPECIALTY CONSUMER CIRCUIT, PDSO16
TDA9898HL/V3 SPECIALTY CONSUMER CIRCUIT, PQFP48
TDA9898HN/V3 SPECIALTY CONSUMER CIRCUIT, PQCC48
TDA9897HL/V3 SPECIALTY CONSUMER CIRCUIT, PQFP48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TDA9888 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB selective AGC amplifier
TDA9888TS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB selective AGC amplifier
TDA9889 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB selective AGC amplifier
TDA9889TS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB selective AGC amplifier
TDA9889TS/V1,512 功能描述:射頻放大器 DVB T AFRIC DOWN CONVERSION RoHS:否 制造商:Skyworks Solutions, Inc. 類型:Low Noise Amplifier 工作頻率:2.3 GHz to 2.8 GHz P1dB:18.5 dBm 輸出截獲點(diǎn):37.5 dBm 功率增益類型:32 dB 噪聲系數(shù):0.85 dB 工作電源電壓:5 V 電源電流:125 mA 測試頻率:2.6 GHz 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*