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參數(shù)資料
| 型號： | TDA9875AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Digital TV Sound Processor DTVSP |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP |
| 文件頁數(shù)： | 36/96頁 |
| 文件大小： | 296K |
| 代理商： | TDA9875AH |
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1999 Dec 20
36
Philips Semiconductors
Product specification
Digital TV Sound Processor (DTVSP)
TDA9875A
10.3.2
G
ENERAL CONFIGURATION REGISTER
Table 16
Subaddress 1 (note 1)
Note
1.
The default setting at power-up is 1100 0000.
BIT
NAME
P2OUT
VALUE
DESCRIPTION
7 (MSB)
This bit controls the general purpose input/output pin P2. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1).
This bit controls the general purpose input/output pin P1. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1). P1OUT is recommended to be
used for switching an SIF trap for the adjacent picture carrier in designs that
employ such a trap.
The IC is in the standby mode. Most functions are disabled and power dissipation
is somewhat reduced, but the analog selectors/matrices remain operational to
support analog copying from SCART-to-SCART.
The IC is in the normal operating mode. On return from standby mode, the device
is in its Power-on reset mode and needs to be re-initialized.
Causes initialization of the TDA9875A to its default settings. This has the same
effect as a Power-on reset. If there is a conflict between the default settings and
any bit set to logic 1 in this register, the bits of this register have priority over the
corresponding default setting.
Automatically reset to logic 0 after initialization. When set to logic 0, the
TDA9875A is in its normal operating mode.
Resets the power fail detector to LOW.
This bit is automatically reset to logic 0 after bit POR in the device status register
has been reset.
A longer decay time is selected for input signals with strong video modulation
(intercarrier). This bit only has an effect when bit AGCOFF = 0.
Selects normal attack and decay times for the AGC.
Forces the AGC block to a fixed gain as defined in the AGC gain register.
The automatic gain control function is enabled and the contents of the AGC gain
register is ignored.
Selects pin SIF2 for input (recommended for satellite tuner).
Selects pin SIF1 for input (terrestrial TV).
6
P1OUT
5
STDBY
1
0
4
INIT
1
0
3
CLRPOR
1
0
2
AGCSLOW
1
0
1
0
1
AGCOFF
0 (LSB)
SIFSEL
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA9875 | Digital TV Sound Processor DTVSP |
| TDA9965 | 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras |
| TDZ10 | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| TDZ11 | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| TDZ12 | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9875AH/V2,557 | 功能描述:IC SOUND PROC DGTL TV 64QFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| TDA9880 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Alignment-free multistandard vision and FM sound IF-PLL demodulator |
| TDA9880T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Alignment-free multistandard vision and FM sound IF-PLL demodulator |
| TDA9881 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Alignment-free vision and FM sound IF PLL demodulator for negative modulated TV standards |
| TDA9881HN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Alignment-free vision and FM sound IF PLL demodulator for negative modulated TV standards |
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