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參數(shù)資料
| 型號： | TDA9850T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | I2C-bus controlled BTSC stereo/SAP decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO32 |
| 封裝： | PLASTIC, SO-32 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 203K |
| 代理商： | TDA9850T |
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1995 Jun 19
8
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled BTSC stereo/SAP decoder
TDA9850
Adjustment procedure
C
OMPOSITE INPUT LEVEL ADJUSTMENT
Feed in from FM demodulator the composite signal with
100% modulation (25 kHz deviation) L + R; f
i
= 300 Hz.
Set input level control via I
2
C-bus monitoring OUTL or
OUTR (500 mV
±
20 mV). Store the setting in a
non-volatile memory.
A
UTOMATIC ADJUSTMENT PROCEDURE
Connect 2.2
μ
F capacitors from ACR and ACL to
ground.
Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel.
Mode selection setting bits: STEREO = 1, SAP = 0
(see Table 8).
Start adjustment by transmission ADJ = 1 in register
ALI3. The decoder will align itself.
After 1 second minimum stop alignment by transmitting
ADJ = 0 in register ALI3 read the alignment data by an
I
2
C-bus read operation from ALR1 and ALR2
(see Chapter “I
2
C-bus protocol”) and store it in a
non-volatile memory. The alignment procedure
overwrites the previous data stored in ALI1 and ALI2.
The capacitors from ACR and ACL may be
disconnected after alignment.
M
ANUAL ADJUSTMENT
Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).
Spectral and wideband data have to be set to 10000
(middle position for adjustment range)
Composite input L = 300 Hz; 14% modulation
Adjust channel separation by varying wideband data
Composite input L = 3 kHz; 14% modulation
Adjust channel separation by varying spectral data
Iterative spectral/wideband operation for optimum
adjustment
Store data in non-volatile memory.
After every power-on, the alignment data and the input
level adjustment data must be loaded from the non-volatile
memory.
T
IMING CURRENT FOR RELEASE RATE
Due to possible internal and external spreading, the timing
current can be adjusted via I
2
C-bus, see Table 9, as
recommended by dbx.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA9851 | I2C-bus controlled economic BTSC stereo decoder |
| TDA9851T | I2C-bus controlled economic BTSC stereo decoder |
| TDA9852 | I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9852H | I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9853 | I2C-bus controlled economic BTSC stereo decoder and audio processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9850TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BTSC/SAP Audio Decoder |
| TDA9851 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled economic BTSC stereo decoder |
| TDA9851T | 制造商:PHILIPS-SEMI 功能描述: |
| TDA9852 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9852H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
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