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參數(shù)資料
| 型號： | TDA9850T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | I2C-bus controlled BTSC stereo/SAP decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO32 |
| 封裝： | PLASTIC, SO-32 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 203K |
| 代理商： | TDA9850T |
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1995 Jun 19
14
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled BTSC stereo/SAP decoder
TDA9850
Notes to the characteristics
1.
Crosstalk:
2.
The transmission contains:
a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics
b) Clock frequency = 50 kHz
c) Repetition burst rate = 400 Hz
d) Maximum bus signal amplitude = 5 V (p-p).
The oscillator is designed to operate together with MURATA resonator CSB503F58 or CSB503JF958 as SMD.
Change of the resonator supplier is possible, but the resonator specification must be close to the specified ones.
The internal SAP carrier level is determined by the composite input level and the level adjustment gain.
When reset is active the SMU-bit (SAP mute) and the LMU-bit (OUTL, OUTR mute) is set and the I
2
C-bus receiver
is in the reset position.
The AC characteristics are in accordance with the I
2
C-bus specification for standard mode (clock frequency
maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated
between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I
2
C-bus specification.
Information about the I
2
C-bus can be found in brochure “I
2
C-bus and how to use it”(order number 9398 393 40011).
3.
4.
5.
6.
Noise detector
f
0
noise band-pass centre
frequency
quality factor
lowest noise threshold
for stereo off respectively
SAP off (RMS value;
see Tables 11 and 12)
highest noise threshold
for stereo off respectively
SAP off (RMS value)
noise threshold step width f
i
= 185 kHz
composite input level
100 mV (RMS)
185
kHz
Q
Ster1,
SAP1
17
6
24
34
mV
f
i
= 185 kHz
Ster16,
SAP16
f
i
= 185 kHz
210
290
400
mV
Ster,
SAP
0
1.5
3
dB
Power-on reset;
note 5
V
RESET(STA)
start of reset voltage
increasing supply voltage
decreasing supply
voltage
increasing supply voltage 5.2
5
2.5
5.8
V
V
4.2
V
RESET(END)
end of reset voltage
6
6.8
V
Digital part (I
2
C-bus pins);
note 6
V
IH
V
IL
I
IH
I
IL
V
OL
HIGH level input voltage
LOW level input voltage
HIGH level input current
LOW level input current
LOW level output voltage
3
0.3
10
10
8.5
+1.5
+10
+10
0.4
V
V
μ
A
μ
A
V
I
IL
= 3 mA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
20 logV
o(rms)
V
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相關代理商/技術參數(shù) |
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|---|---|
| TDA9850TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BTSC/SAP Audio Decoder |
| TDA9851 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled economic BTSC stereo decoder |
| TDA9851T | 制造商:PHILIPS-SEMI 功能描述: |
| TDA9852 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9852H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
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