- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383990 > TDA9850T (NXP SEMICONDUCTORS) I2C-bus controlled BTSC stereo/SAP decoder PDF資料下載
參數(shù)資料
| 型號： | TDA9850T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | I2C-bus controlled BTSC stereo/SAP decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO32 |
| 封裝： | PLASTIC, SO-32 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 203K |
| 代理商： | TDA9850T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
1995 Jun 19
11
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled BTSC stereo/SAP decoder
TDA9850
CHARACTERISTICS
All voltages are measured relative to GND; V
CC
= 9 V; R
s
= 600
; R
L
= 10 k
; AC-coupled; C
L
= 2.5 nF; f
i
= 1 kHz;
T
amb
= +25
°
C; see Fig.1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
CC
V
ripple(p-p)
supply voltage
allowed supply voltage
ripple (peak-to-peak
value)
supply current
internal reference voltage
at pin V
ref
crosstalk between bus
inputs and signal outputs
8.5
9
9.5
100
V
mV
f
i
= 50 Hz to 100 kHz
I
CC
V
ref
58
3.7
75
mA
V
α
ct
notes 1 and 2
110
dB
Input level adjustment control
G
LA
input level adjustment
control
step resolution
maximum input voltage
level (RMS value)
input impedance
3.5
+4.0
dB
G
step
V
i(rms)
2
0.5
dB
V
Z
i
29.5
35
40.5
k
Stereo decoder
MPX
L+R
input voltage level for
100% modulation L + R;
25 kHz deviation
(RMS value)
input voltage level for
100% modulation L
R;
50 kHz deviation
(peak value)
maximum headroom for
L + R, L, R
nominal stereo pilot
voltage level (RMS value)
pilot threshold voltage
stereo on (RMS value)
input level adjusted via
I
2
C-bus (L + R;
f
i
= 300 Hz); monitoring
OUTL or OUTR
250
mV
MPX
L
R
707
mV
MPX
(max)
f
mod
< 15 kHz;
THD < 15%
9
dB
MPX
pilot
50
mV
ST
on(rms)
data STS = 1
data STS = 0
data STS = 1
data STS = 0
15
10
480
2.5
500
35
30
520
mV
mV
mV
mV
dB
mV
ST
off(rms)
pilot threshold voltage
stereo off (RMS value)
Hys
OUT
L+R
hysteresis
output voltage level for
100% modulation L + R at
OUTL, OUTR
input level adjusted via
I
2
C-bus (L + R;
f
i
= 300 Hz); monitoring
OUTL or OUTR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA9851 | I2C-bus controlled economic BTSC stereo decoder |
| TDA9851T | I2C-bus controlled economic BTSC stereo decoder |
| TDA9852 | I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9852H | I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9853 | I2C-bus controlled economic BTSC stereo decoder and audio processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9850TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BTSC/SAP Audio Decoder |
| TDA9851 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled economic BTSC stereo decoder |
| TDA9851T | 制造商:PHILIPS-SEMI 功能描述: |
| TDA9852 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| TDA9852H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。