參數(shù)資料
型號(hào)： TDA9331H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： I2C-bus controlled TV display processors
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 33/56頁(yè)
文件大?。?/td> 228K
代理商： TDA9331H
2000 May 08
33
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
a) For picture tubes with Dynamic Astigmatic Focusing (DAF) guns, the rise of the EHT voltage between
75 and 100% is preferred to be even slower than the rise time from 0 to 75%. This can be realized by activating
bit ESS, at which the total switch-on time of the horizontal output pulse is approximately 1175 ms.
b) During switch-off, the slow-stop function is active. This is realized by decreasing the t
on
of the output transistor
complementary to the start-up behaviour. The switch-off time is approximately 50 ms. The slow-stop procedure
is synchronized to the start of the first new vertical field after reception of the switch-off command. During the
slow-stop period, the fixed beam current switch-off can be activated (see also note 23). This current is active
during a part of the slow stop period, see Fig.15.
c) The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched
on during the flyback pulse. This protection is not active during the switch-on or switch-off period.
36. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
37. The rise and fall times of the blanking pulse and clamping pulse at the sandcastle output (pin 9) depend on the
capacitive load. The value of the source current during the rising edge or sink current during the falling edge is
0.7 mA (typical value).
38. The vertical guard pulse from the vertical output stage should fall within the vertical blanking period
(see Figs 12 and 13) and should have a width of at least one line period. For the detection of a missing pulse, a guard
current value of 1 mA during normal operation is sufficient. If the RGB outputs must also be blanked if the guard pulse
lasts longer than the vertical blanking period, the guard current must have a value between 2.6 mA and 3.5 mA.
39. Switching between the 1f
V
or the 2f
V
mode is realized via bit SVF.
40. The vertical linearity is measured on the differential output current at the vertical drive output (pins 1 and 2) for zero
S-correction. The linearity is defined as the ratio of the upper and lower half amplitudes at the vertical output. The
upper amplitude is measured between lines 27 and 167, the lower amplitude between lines 167 and 307 for a 50 Hz
video signal.
41. The field detection mechanism is explained in Fig.17.
a) The incoming V
D
pulse is synchronized with the internal clock signal CK2H that is locked to the incoming H
D
pulse. If the synchronized V
D
pulse of a field coincides with the internally generated horizontal blanking signal
HBLNK,thenthisisfield 1.IfthesynchronizedV
D
pulsedoesnotcoincide withHBLNK,thenthisisfield 2.Signals
CK2H and HBLNK are both output signals of the horizontal divider circuit that is part of the line-locked clock
generator. A reliable field detection is important for correct interlacing and de-interlacing and for the correct timing
of the measurement lines of the black current loop. For the best noise margin, the edges of the V
D
pulse should
be on approximately
1
4
and
3
4
of the line, referred to the rising edges of the H
D
input signal.
b) If bus bit VSR = 0, the end of the V
D
pulse is used as reference for both field detection and start of vertical scan.
If VSR = 1, the starting edge is used.
42. Output range percentages mentioned for E-W control parameters are based on the assumption that the E-W
modulator is dimensioned such that 400
μ
A variation in E-W output current of the IC is equivalent to 20% variation
in picture width. In VGA mode, the E-W output current is proportional to the applied line frequency.
43. The IC has protection inputs for flash protection and overvoltage protection.
a) The flash protection input is used to switch the horizontal drive output off immediately if a picture tube flashover
occurs, to protect the line output transistor. An external flash detection circuit is needed. When the flash input is
pulled HIGH, the horizontal output is switched off and status bit FLS is set. When the input turns LOW again, the
horizontal output is switched on immediately without I
2
C-bus intervention via the slow start procedure.
b) The overvoltage (X-ray) protection is combined with the EHT compensation input. When this protection is
activated, the horizontal drive can be directly switched off (via the slow stop procedure). It is also possible to
continue the horizontal drive and only set status bit XPR in output byte 01 of the I
2
C-bus. The choice between the
two modes of operation is made via bit PRD.
44. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason, an extra DAC
is included in the vertical amplitude control, which controls the vertical scan amplitude between 0.75 and 1.38 of the
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