參數(shù)資料
型號(hào)： TDA9331H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： I2C-bus controlled TV display processors
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 30/56頁(yè)
文件大小： 228K
代理商： TDA9331H
2000 May 08
30
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
c) The signal amplitude at the RGB outputs of the TDA933xH depends on the gain of the RGB amplifiers. The gain
of the RGB amplifiers should be 35 to get the nominal signal amplitude of 2 V (b-w) at the RGB outputs for a
cathode drive level of 70 V (b-w) and the nominal setting of the drive level bits (CL
3210
= 1000, see Table 15).
12. The bandwidth of the video channels depends on the capacitive load at the RGB outputs. For 2f
H
or VGA
applications, external (PNP) emitter followers on the RGB outputs of the TDA933xH are required, to avoid reduction
of the bandwidth by the capacitance of the wiring between the TDA933xH and the RGB power amplifiers on the
picture tube panel. If emitter followers are used, it should be possible to obtain the bandwidth figures that are
mentioned for 10 pF load capacitance.
13. The timing of the horizontal blanking pulse on the RGB outputs is illustrated in Fig.10.
a) The start of the blanking pulse is determined by an internal counter blanking that starts 40 LLC (line locked clock)
pulses before the centre of the horizontal flyback pulse. This is 5.8
μ
s for 1fH and 2.9
μ
s for 2fH TV mode. The
end of the blanking is determined by the trailing edge of the flyback pulse. If required, the start of the counter
blanking can be adjusted in 15 steps with bus bits LBL3 to LBL0. This can be useful when HDTV or VGA signals
are applied to the IC.
b) When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by reducing the horizontal scan
amplitude, the edges of the picture may be slightly disturbed. This effect can be prevented by adding an additional
blanking pulse to the RGB signals. This blanking pulse is derived from the horizontal oscillator and is directly
related to the incoming H
D
pulse (independent of the flyback pulse). The additional blanking pulse overlaps the
normal blanking signal by approximately 1
μ
s (1f
H
) or 0.5
μ
s (2f
H
) on both sides. This wide blanking is activated
by bit HBL. The phase of this blanking can be controlled in 15 steps by bits HB3 to HB0.
14. When a YUV or RGB signal is applied to the IC and no separate horizontal or vertical timing pulses are available, an
external sync separator circuit is needed. The TDA933xH has an edge triggered phase detector circuit on the H
D
input that uses the start of the H
D
pulse as timing reference. To avoid horizontal phase disturbances during the
vertical blanking period, it is important that the sync separator does not generate extra horizontal sync pulses during
the vertical sync pulse on the video signal.
15. Start-up behaviour of the CCC loop. After the horizontal output is released via bits STB, the RGB outputs are blanked
and the CCC loop is activated. Because the picture tube is cold, the measured cathode currents are too small, and
both gain and offset are set at the maximum value so that the CCC loop gets out of range and status bit BCF is set
to 1. Once the picture tube is warm, the loop comes within range and the set signal for bit BCF is removed. Status
bit BCF is set if the voltage of at least one of the cut-off measurement lines at the RGB outputs is lower than 1.5 V
or higher than 3.5 V. The RGB outputs are unblanked as soon as bit BCF changes from 1 to 0. To avoid a bright
picture after switch-on with a warm picture tube, reset of bit BCF is disabled for 0.5 s after switch-on of the horizontal
output. If required, the blanking period of the RGB outputs can be increased by forcing the blanking level at the RGB
outputs via RBL = 1. When status bit BCF changes from 1 to 0, bit RBL can be set to 0 after a certain waiting period.
16. Voltage V
g2
of the picture tube can be aligned with the help of status bits WBC and HBC. Bit WBC becomes 1 if the
lowest of the three RGB output voltages during the cut-off measurement lines is within the alignment window of
±
0.1 V around 2.5 V. Bit HBC is 0 if the lowest cut-off level is below 2.6 V, and 1 if this level is above 2.6 V.
a) Voltage V
g2
should be aligned such that bit WBC becomes 1. If bit WBC is 0, bit HBC indicates in which direction
voltage V
g2
should be adjusted. If bit HBC = 0, the DC level at the RGB outputs of the IC is too low and voltage
V
g2
should be adjusted lower until bit WBC becomes 1. If HBC = 1, the DC level is too high and voltage V
g2
should
be adjusted higher until bit WBC becomes 1.
b) It should be noted that bit WBC is only meant for factory alignment of voltage V
g2
. If the value of bit WBC depends
on the video content, this is not a problem. Correct operation of the black current loop is guaranteed as long as
status bit BCF = 0, meaning that the DC level of the measurement lines at the RGB outputs of the IC is between
1.5 and 3.5 V.
17. Signal-to-noise ratio (S/N) is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 10 MHz).
18. This is a current input. When the black current feedback loop is closed (only during measurement lines or during fixed
beam current switch off), the voltage at this pin is clamped at 3.3 V. When the loop is open circuit, the input is not
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