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參數(shù)資料
| 型號： | TDA9331H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | I2C-bus controlled TV display processors |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 10/56頁 |
| 文件大?。?/td> | 228K |
| 代理商： | TDA9331H |
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2000 May 08
10
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
The IC has an EHT compensation input which controls
both the vertical and the E-W output signals. The relative
control effect on both outputs can be adjusted via the
I
2
C-bus (sensitivity of vertical correction is fixed; E-W
correction variable).
Toavoiddamagetothepicturetubeintheeventofmissing
or malfunctioning vertical deflection, a vertical guard
function is available at the sandcastle pin (pin SCO). The
vertical guard pulse from the vertical output stage
(TDA835x) should be connected to the sandcastle pin,
which acts as a current sense input. If the guard pulse is
missing or lasts too long, bit NDF is set in the status
register and the RGB outputs are blanked. If the guard
function is disabled via bit EVG, only NDF status bit NHF
is set.
TheICalsohasinputsforflashandovervoltageprotection.
More details about these functions are given in Chapter
“Characteristics”; note 43.
I
2
C-BUS SPECIFICATION
The slave address of the IC is given in Table 1. The circuit
operates up to clock frequencies of 400 kHz. Valid
subaddresses: 00 to 1F, subaddress FE is reserved for
test purposes. The auto-increment mode is available for
subaddresses.
Table 1
Slave address (8C)
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
1
0
1/0
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