參數(shù)資料
型號： TDA9113
廠商： STMICROELECTRONICS
元件分類： 偏轉(zhuǎn)
英文描述： HORIZ/VERT DEFLECTION IC, PDIP32
封裝： SHRINK, PLASTIC, DIP-32
文件頁數(shù)： 25/50頁
文件大小： 755K
代理商： TDA9113
TDA9113
31/50
regulation) and at 1 for separated architecture (B+
and EHT each regulated separately).
Figure 10. Control of HOut and BOut at start/stop at nominal Vcc
9.4 - VERTICAL SECTION
9.4.1 - General
The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of de-
flection frequency, on which vertical geometry cor-
rections of C- and S-type are superimposed (see
chapter TYPICAL OUTPUT WAVEFORMS).
Block diagram is in Figure 11. The sawtooth is ob-
tained by charging an external capacitor on pin
VCap with controlled current and by discharging it
via transistor Q1. This is controlled by the CON-
TROLLER. The charging starts when the voltage
across the capacitor drops below VVOB threshold.
The discharging starts either when it exceeds VVOT
threshold or a short time after arrival of synchroni-
zation pulse. This time is necessary for the AGC
loop to sample the voltage at the top of the saw-
tooth. The VVOB reference is routed out onto VO-
scF pin in order to allow for further filtration.
The charging current influences amplitude and
shape of the sawtooth. Just before the discharge,
the voltage across the capacitor on pin VCap is
sampled and stored on a storage capacitor con-
nected on pin VAGCCap. During the following ver-
tical period, this voltage is compared to internal
reference REF (VVOT), the result thereof control-
ling the gain of the transconductance amplifier pro-
viding the charging current. Speed of this AGC
loop depends on the storage capacitance on pin
VAGCCap. The VLock I2C bus flag is set to 1
when the loop is stabilized, i.e. when the voltage
on pin VAGCCap matches VVOT value. On the
screen, this corresponds to stabilized vertical size
of picture. After a change of frequency on the
sync. input, the stabilization time depends on the
frequency difference and on the capacitor value.
The lower its value, the shorter the stabilization
time, but on the other hand, the lower the loop sta-
bility. A practical compromise is a capacitance of
470nF. The leakage current of this capacitor re-
sults in difference in amplitude between low and
high frequencies. The higher its parallel resistance
RL(VAGCCap), the lower this difference.
When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency fVO(0) only depends on the
value of the capacitor on pin VCap. It can be
roughly calculated using the following formula
fVO(0) =
t
V(HPosF)
Soft start
Soft stop
Normal operation
Start
HOut
Start
BOut
Stop
HOut
Stop
BOut
HOut
H-duty cycle
BOut (positive)
B-duty cycle
100%
0%
VHOn
VBOn
VHBNorm
VHPosMax
VHPosMin
HPOS (I2C)
range
minimum value
maximum value
C(VCap)
. 100Hz
150nF
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