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參數(shù)資料
| 型號(hào)： | TDA9113 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | SHRINK, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 21/50頁 |
| 文件大小： | 755K |
| 代理商： | TDA9113 |
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TDA9113
28/50
band even while locked. The speed of the PLL1
depends on the current value provided by the
charge pump. While not locked, the current is very
low, to slow down the changes of VCO frequency
and thus protect the external power components
at sync. signal change. In locked state, the cur-
rents are much higher, two different values being
selectable via PLL1Pump I2C bus bit to provide a
mean to control the PLL1 speed by S/W. Lower
values make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depends on the choice of ex-
ternal components making up the loop filter. A
“CRC” filter is generally used (see Figure 4 on
page 28).
Figure 4. H-PLL1 filter configuration
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into ac-
count missing or wrong pulses on the phase com-
parator. Inhibition is obtained by forcing the charge
pump output to high impedance state. The inhibi-
tion
mechanism
can
be
disabled
through
PLL1Pump I2C bus bit.
The Figure 7, in its upper part, shows the position
of the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control
HPOS.
Figure 5. Horizontal PLL1 block diagram
HPLL1F
9
R2
C1
C2
4
Lock
Status
PLL
INHIBITION
HPosF
Low
High
LOCK
COMP
CHARGE
PUMP
HPLL1F R0
C0
86
VCO
HOSC
(I2C)
HPOS
INPUT
INTERFACE
H/HVSyn
Sync
9
10
PLL1Pump
V-sync (extracted)
PLL1InhEn
(I2C)
HOscF
DETECTOR
1
Polarity
V-sync
Extracted
REF1
(pin & I2C)
(I2C)
0
PLL1
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