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| 型號： | TDA8754EL/14 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
| 封裝： | 17 X 17 MM, 1.05 MM HEIGHT, LOW PROFILE, PLASTIC, SOT-774-1, MO-192, BGA-208 |
| 文件頁數(shù)： | 7/57頁 |
| 文件大小： | 264K |
| 代理商： | TDA8754EL/14 |
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9397 750 14984
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 06 — 16 June 2005
15 of 57
Philips Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msps
The reference ladders regulators are integrated.
8.2.4 Clamp
Three independent parallel clamping circuits are used to clamp the video input signals on
programmable black levels. The clamp levels may be set from
24 to +136 LSBs in steps
of 1 LSB. They are controlled by three 9-bit I2C-bus registers (OFFSETR, OFFSETG and
OFFSETB).
The clamp pulse can be generated internally (based on the PLL clock reference) or can
be externally applied on pin CLP.
By setting correctly the I2C-bus bits, it is possible to inhibit the clamp request with the
Vsync signal. This inhibition will be effected by forcing logic 0 on the clamp request output.
It should be noted that the clamp period can start on the falling edge of the clamp request
and that the high level of the clamp request sets the ADC outputs in the blanking mode.
This means that by forcing the clamp signal request to logic 0 by using Vsync, a falling
edge may happen on the clamp request if this signal was at logic 1 before enforcing the
inhibition. To avoid this, the user has to guarantee that the Vsync signal used for the clamp
inhibition will not be set during a high level of the clamp request signal.
Remark: If signal Vsync is coming from the external pin VSYNC, this signal may be used
to coast the PLL. In order to properly do the coast, the edge of signal Vsync (COAST)
must not appear at the same time as the edge of signal Hsync. This condition is similar to
the pin CLP inhibition condition.
8.2.5 AGC
Three independent variable gain ampliers are used to provide, for each channel, a
full-scale input signal to the 8-bit ADC. The gain adjustment range is designed in such a
way that for an input range varying from 0.5 to 1 V (p-p), the output signal corresponds to
the ADC full-scale input of 1 V (p-p).
8.3 HSOSEL, DEO and SCHCKREFO
Bit HSOSEL allows to have a full correlation phase behavior between outputs CKDATA
and HSYNCO when bit HSOSEL = 0 (Hsync from counter). If HSOSEL = 0 and bits PA4
to PA0 of register PHASE are changed to chose the best sampling time, the phase
relationship between outputs CKDATA and HSYNCO will stay unchanged. After the video
standard is determined, bit HSOSEL must be set to a logic 0 for normal operation mode.
To use the Hsync from the counter the registers HSYNCL, HBACKL, HDISPLMSB and
HDISPLLSB should be set properly in order to create the correct HSYNCO and DEO
output signals (see Figure 5 and Figure 6), which is depending on video standard. Output
signal DEO should be used to determine the rst active pixel.
The demultiplexed mode should be used (bit DMX = 1) and the output ow is alternated
between port A and port B in case the sampling frequency is over 140 Msample/s (clock
frequency). It is necessary, in order to warrant that the outputs HSYNCO and DEO are
always changing on CKDATA output rising edge (see Figure 7), that the values HSYNCL,
HBACKL and HDISPL (see Figure 5) are even value. If an odd value is entered the
outputs HSYNCO and DEO can change state during falling edge, which is not compliant
with the th(o) and td(o) specied output timing.
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| TDA8754HL/14 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
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| TDA8754EL/21 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
| TDA8754HL/11 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| TDA8754EL/11 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TDA8754H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple high speed ADC for LCD drive |
| TDA8754HL/11/C1,51 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 3X8 BIT VIDEO RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TDA8754HL/11/C1,55 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 TRPL 8BIT VIDEO ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TDA8754HL/11/C1/R1 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 3X8-BIT VID INTERFACE 110 MSPS RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TDA8754HL/11/C1/R1,518 | 制造商:NXP Semiconductors 功能描述: |
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