參數(shù)資料
型號: TDA8754EL/14
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208
封裝: 17 X 17 MM, 1.05 MM HEIGHT, LOW PROFILE, PLASTIC, SOT-774-1, MO-192, BGA-208
文件頁數(shù): 24/57頁
文件大小: 264K
代理商: TDA8754EL/14
9397 750 14984
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 06 — 16 June 2005
30 of 57
Philips Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msps
9.10 Horizontal sync registers
Remark: The sum of HSYNCL[9:0] + HBACKL[9:0] + HDISPL[9:0] + 16 needs to be
smaller than the PLL divider.
Table 36:
DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DI7
DI6
DI5
DI4
DI3
DI2
DI1
D0
Reset
10011000
Access
WWWWWWWW
Table 37:
DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit description
Bit
Symbol
Description
7 to 0
DI[7:0]
PLL divider ratio; these are the 8 LSBs of the 12-bit value; see Table 38
Table 38:
PLL divider ratio
DI11
VDI10
VDI9
VDI8
VDI7
VDI6
VDI5
VDI4
DI3
DI2
DI1
DI0
PLL divider ratio
0
000110
0100100
:
::::::
::::
1
111111
1111
4095
Table 39:
HSYNCL, HBACKL and HDISPL (address 0Eh, 0Fh, 10h, 11h) bit allocation
7
6
5
4
3
2
1
0
Register address 0Eh
HSYNCL9
HSYNCL8
HSYNCL7
HSYNCL6
HSYNCL5
HSYNCL4
HSYNCL3
HSYNCL2
00100100
Register address 0Fh
HSYNCL1
HSYNCL0
HBACKL9
HBACKL8
HBACKL7
HBACKL6
HBACKL5
HBACKL4
00001111
Register address 10h
HBACKL3
HBACKL2
HBACKL1
HBACKL0
HDISPL11
HDISPL10
HDISPL9
HDISPL8
10000101
Register address 11h
HDISPL7
HDISPL6
HDISPL5
HDISPL4
HDISPL3
HDISPL2
HDISPL1
HDISPL0
00000000
Table 40:
Sync registers (0Eh to 11h) bit description
Bit
Symbol
Description
9 to 0
HSYNCL[9:0] length of the Hsync signal; in number of pixel clock cycles; minimum value is 16
9 to 0
HBACKL[9:0]
interval between the Hsync active edge and the rst active pixel; in number of pixels; minimum
value is 16
11 to 0 HDISPL[11:0] number of active pixels for one line; length of the data enable signal; minimum value is 16
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