參數(shù)資料
型號: TDA7503
廠商: STMICROELECTRONICS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁數(shù): 28/30頁
文件大?。?/td> 297K
代理商: TDA7503
7/30
TDA7503
56
VSS5
GND
VSS
Power Ground.
57
VDD5
PWR
VDD
3.3V Power Supply.
58
SRA_D4/DRA0
I/O
O, High
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 4/DSP DRAM
Address Line 0. When in SRAM Mode these pins act as
the EMI multiplexed address and data line 4. When in
DRAM Mode they act as the EMI address line 0.
59
SRA_D5/DRA1
I/O
O, High
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 5/DSP DRAM
Address Line 1. When in SRAM Mode these pins act as
the EMI multiplexed address and data line 5. When in
DRAM Mode they act as the EMI address line 1.
60
SRA_D6/DRA2
I/O
O, High
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 6/DSP DRAM
Address Line 2. When in SRAM Mode these pins act as
the EMI multiplexed address and data line 6. When in
DRAM Mode they act as the EMI address line 2.
61
SRA_D7/DRA3
I/O
O, High
200pF
8mA
DSP SRAM Multiplexed Address/Data Line 7/DSP DRAM
Address Line 3. When in SRAM Mode these pins act as
the EMI multiplexed address and data line 7. When in
DRAM Mode they act as the EMI address line 3.
62
DBSEL
I
4mA
Debug Port MUX Selection. Selects either DSP0 or DSP1
to be connected to the Debug Port pins.
63
DBRQN
I
4mA
Debug Port Request Input. Means of entering the Debug
mode of operation.
64
DBIN/OS0
I/O
I
100pF
4mA
Debug Port Serial Input/Chip Status 0. The serial data
input for the Debug Port is provided when an input. When
an output, together with OS1 provides information about
the chip status. Can also be used as GPIO for the MX51.
65
DBCK/OS1
I/O
I
100pF
4mA
Debug Port Bit Clock/Chip Status 1. The serial clock for
the Debug Port is provided when an input. When an
output, together with OS0 provides information about the
chip status. Can also be used as GPIO for the MX51.
66
DBOUT
I/O
I
100pF
4mA
Debug Port Serial Output. The serial data output for the
Debug Port. Can also be used as a GPIO for the MX51.
67
SCANEN
I
4mA
SCAN Enable. Enable SCAN Path and MUXing of
SCANIN and SCANOUT Pins.
68
TESTEN
I
4mA
Test Enable. Enable Scan Mode Clocks. An active low
signal will enable the same clock to all scan chains. This
pin also makes all latches transparent.
69
PVCC
I
AVCC
PLL Clock Power Supply . Vdd Pin for PLL Clock
Oscillator.
70
PGND
I
AGND
PLL Clock Ground Input. Ground connection for oscillator
circuit.
71
CLKOUT
O
200pF
8mA
Clock Output (Output). Clock output from an internal
divide of the VCO clock. This output can be disabled and
the divide factor is programmable.
72
XTI
I
OSCIN Crystal Oscillator Input. External Clock Input or crystal
connection.
73
XTO
O
High
50pF
OSCOUT Crystal Oscillator Output. Crystal Oscillator output drive.
PIN DESCRIPTION (continued)
N.
Name
Type
Reset
Status
O/P
Load
Buffer
Function
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