參數(shù)資料
型號(hào)： TDA7503
廠商： STMICROELECTRONICS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 11/30頁(yè)
文件大小： 297K
代理商： TDA7503
19/30
TDA7503
EXTERNAL MEMORY INTERFACE (EMI) DRAM MODE
Note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6.
DRAM Refresh Timing
Note: 1. Happens when a Refresh Cycle is followed by an Access Cycle.
Characteristics
Timing
Mode
42MHz
Unit
Min.
Max.
Page Mode Cycle Time
slow
fast
100
75
–
ns
RAS or RD Assertion to Data Valid
slow
fast
–
159
109
ns
CAS Assertion to Data Valid
slow
fast
–
65
40
ns
Column Address Valid to Data Valid
slow
fast
–
80
55
ns
CAS Assertion to Data Active
0
–
ns
RAS Assertion Pulse Width (Note 1)(Page Mode Access Only)
slow
fast
264
189
–
ns
RAS Assertion Pulse Width (Single Access Only)
slow
fast
164
114
–
ns
RAS or CAS Negation to RAS Assertion
slow
fast
120
70
–
ns
CAS Assertion Pulse Width
slow
fast
65
40
–
ns
Last CAS Assertion to RAS Negation (Page Mode Access Only)
slow
fast
60
35
–
ns
Characteristics
Timing
Mode
42MHz
Unit
Min.
Max.
RAS Negation to RAS Assertion
slow
fast
143
93
–
ns
CAS Negation to CAS Assertion
slow
fast
118
68
–
ns
Refresh Cycle Time
slow
fast
325
225
–
ns
RAS Assertion Pulse Width
slow
fast
166
116
–
ns
RAS Negation to RAS Assertion for Refresh Cycle (Note 1)
slow
fast
120
70
–
ns
CAS Assertion to RAS Assertion on Refresh Cycle
18
–
ns
RAS Assertion to CAS Negation on Refresh Cycle
slow
fast
160
110
–
ns
RAS Negation to CAS Assertion on a Refresh Cycle
slow
fast
114
64
–
ns
CAS Negation to Data Not Valid
0
–
ns
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