參數(shù)資料
型號(hào)： TDA5251F1
廠商： INFINEON TECHNOLOGIES AG
英文描述： ASK/FSK 315MHz Wireless Transceiver
中文描述： 詢價(jià)/ FSK信號(hào)315MHz的無(wú)線收發(fā)器
文件頁(yè)數(shù)： 32/88頁(yè)
文件大?。?/td> 2086K
代理商： TDA5251F1
TDA5251 F1
Version 1.0
Functional Description
Preliminary Specification
32
2003-02-18
Confidential
data_valid.wmf
Figure 2-13
Data Valid Circuit
D_OUT and RX_DATA_INV from the CONFIG register determine the output of data at Pin 28.
RxTxint
and TX_ON are internally generated signals.
In RX and power down mode Data pin (Pin 28) is tied to GND.
data_switch.wmf
Figure 2-14
Data Input/Output Circuit
2.4.18
Sequence Timer
The sequence timer has to control all the enable signals of the analog components inside the chip.
The time base is the 32 kHz RC oscillator.
After the first POWER ON or RESET a 730kHz clock is available at the clock output pin. This clock
output can be used by an external P to set the system into the desired state and outputs valid data
after 500 μs (see
Figure 2-15
and
Figure 2-16
, tCLKSU)
There are two possibilities to start the device after a reset or first power on:
PWDDD pin is LOW: Normal operation timing is performed after t
SYSSU
(see
Figure 2-15
).
PWDDD pin is HIGH (device in power down mode): A clock is offered at the clock output pin
until the device is activated (PWDDD pin is pulled to LOW). After the first activation the time
t
SYSSU
is required until normal operation timing is performed (see
Figure 2-16
).
This could be used to extend the clock generation without device programming or activation.
Note:
It is
required
to activate the device for the duration of t
SYSSU
after first power on or a reset.
Only if this is done the normal operation timing is performed.
0,5*TH1
T
GATE
0,5*TH2
DATA VALID
TH1 T
GATE
TH2
RSSI TH3
Data
DATA VALID
D_OUT
RX DATA
RX_DATA_INV
TX DATA
TX ON
RxTxint
28
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