參數(shù)資料
型號: TDA5251F1
廠商: INFINEON TECHNOLOGIES AG
英文描述: ASK/FSK 315MHz Wireless Transceiver
中文描述: 詢價/ FSK信號315MHz的無線收發(fā)器
文件頁數(shù): 31/88頁
文件大?。?/td> 2086K
代理商: TDA5251F1
TDA5251 F1
Version 1.0
Functional Description
Preliminary Specification
31
2003-02-18
Confidential
Note:
The time delay between start of ON time and the 15μs LOW impulse is 2.6ms + 3 period of
data rate.
If ADC & Data Detect Logic are in continuous mode the 15μs LOW impulse is applied at
PwdDD
after each data valid decision.
In self polling mode if D9=0 (Register 00h) and when
PwdDD
pin level is HIGH the CLK output is
on during ON time and off during OFF time. If D9=1, the CLK output is always on.
TIMER MODE:
Only the internal Timer (determined by the
ON_TIME
and
OFF_TIME
registers) is
active to support an external logic with periodical Interrupts. After ON_TIME + OFF_TIME a 15μs
LOW impulse is applied at the
PwdDD
pin (Pin 27).
timing_timermode.wmf
Figure 2-11
Timing for Timer Mode
2.4.17
Data Valid Detection, Data Pin
Data signals generate a typical spectrum and this can be used to determine if valid data is on air.
data_rate_detect.wmf
Figure 2-12
Frequency and RSSI Window
The “data valid” criterion is generated from the result of RSSI-TH3 comparison and t
GATE
between
TH1 and TH2 result as shown below. In case of Manchester coding the 0,5*TH1 and 0,5*TH2 gives
improved performance.
The use of permanent data valid recognition makes it absolutely necessary to set the RSSI-ADC
and the Window counter into continuous mode (Register 00H, Bit D5 = D6 = 1).
Action
Register 04H
OFF_TIME
t
Register 04H
ON_TIME
ON_TIME
PwdDD pin in
TIMER MODE
t
15μs
15μs
Register 05H
Amplitude
Frequency
RSSI
no DATA on air
DATA on air
Frequency & RSSI Window
f
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