參數(shù)資料
型號(hào): TDA5251F1
廠(chǎng)商: INFINEON TECHNOLOGIES AG
英文描述: ASK/FSK 315MHz Wireless Transceiver
中文描述: 詢(xún)價(jià)/ FSK信號(hào)315MHz的無(wú)線(xiàn)收發(fā)器
文件頁(yè)數(shù): 23/88頁(yè)
文件大小: 2086K
代理商: TDA5251F1
TDA5251 F1
Version 1.0
Functional Description
Preliminary Specification
23
2003-02-18
Confidential
The I
2
C / 3-wire Bus Interface gives an external microcontroller full control over important system
parameters at any time.
It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer
Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A
detailed description is given in
Section 2.4.16
.
The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold
comparator. The window counter uses the incoming data signal from the data slicer as the gating
signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The
result is compared with the expected datarate.
The threshold comparator compares the actual RSSI level with the expected RSSI level.
If both conditions are true the
PwdDD
pin is set to LOW in self polling mode as you can see in
Section 2.4.16
. This signal can be used as an interrupt for an external μP. Because the
PwdDD
pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an
external LOW thus enabling the device.
2.4.15
The TDA5251 supports the I
2
C bus protocol (2 wire) and a 3-wire bus protocol. Operation is
selectable by the
BusMode
pin (pin 2) as shown in the following table. All bus pins (BusData,
BusCLK,
EN
, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional
where the output is open drain driven by an internal 15k pull up resistor.
Bus Interface and Register Definition
i2c_3w_bus.wmf
Figure 2-7
Bus Interface
Note:
The Interface is able to access the internal registers at any time, even in POWER DOWN
mode. There is no internal clock necessary for Interface operation.
Table 2-6
Function
I
2
C Mode
3-wire Mode
Bus Interface Format
BusMode
EN
BusCLK
Clock input
BusData
Data in/out
Low
High
High= inactive,
Low= active
I
2
C / 3-wire
INTERFACE
INTERNAL BUS
BusData
BusCLK
BusMode
1 1 1 0 0 0 0 0
CHIP ADDRESS
F
16
17
EN
24
2
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