參數(shù)資料
型號(hào)： TDA4885
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： 150 MHz video controller with I2C-bus
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP32
封裝： 0.400 INCH, PLASTIC, SOT-232-1, SDIP-32
文件頁(yè)數(shù)： 17/56頁(yè)
文件大?。?/td> 396K
代理商： TDA4885
1997 Nov 25
17
Philips Semiconductors
Product specification
150 MHz video controller with I
2
C-bus
TDA4885
Notes to the characteristics
1.
Definition of levels (see Figs 3 to 5):
Reference black level
:this is the level to which the input level is clamped during the input clamping pulse
(V
5
> 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs:
a) when the input is at black and the brightness setting is nominal (subaddress 01H = 10H)
b) during output blanking/clamping (V
11
> 3.5 V) if control bit PEDST = 0.
Video black level
:this is the black level of the actual video. On the input it is still equal to the reference black level.
On the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level
unaltered.
Pedestal black level
:this is an ultra black level which deviates from reference black level by a fixed amount. It can
be observed on the output during output blanking/clamping (V
11
> 3.5 V) if control bit PEDST = 1.
Switch-off voltage
: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the
internal black level storage capacitors if the supply voltage is less than V
PSO
.
Blanking level
: this level equals reference black (control bit PEDST = 0) or pedestal black (control bit PEDST = 1).
2.
Explanation to black level adjustment:
The actual blanking level on the output depends on the external feedback application. The loop will only function
correctly if it is within the control range of V
30, 25, 20rbl(min)
to V
30, 25, 20rbl(max)
. Note: changing control bit PEDST in a
given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three
black levels).
The three reference black levels are aligned correctly when they are made equal to the ‘extended cut-off levels’ of
the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying
a negative pulse to grid 1.
t
d11(clamp)t
delay between clamping input
at pin 11 (trailing edge) and
end of internal output clamping
pulse
see Fig.8
60
ns
I
2
C-bus inputs (pins 15 and 16)
f
SCL
V
IL
V
IH
I
IL
I
IH
V
OL
I
ack
SCL clock frequency
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
LOW-level output voltage
output current at pin 15 during
acknowledge
threshold for power-on reset on rising supply voltage
0.0
3.0
0.0
3.0
100
1.5
5.0
10
10
0.4
5.0
kHz
V
V
μ
A
μ
A
V
mA
V
IL
= 0 V
V
IH
= 5 V
during acknowledge
V
OL
= 0.4 V
V
th(POR)(r)
1.5
3.5
1.5
2.0
7.0
V
V
V
V
falling supply voltage
V
th(POR)(f)
threshold for power-on reset off rising supply voltage
falling supply voltage
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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